Moreau Mathieu

Prénom : Mathieu
Nom : Moreau
Liste de Publications 2009-2013 :
D. Munteanu, M. Moreau, and J. L. Autran, “A Compact Model for the Ballistic Subthreshold Current
in Ultra-Thin Independent Double-Gate MOSFETs”, Molecular Simulation, Vol. 35, No. 6, 2009, pp.
491-497. (doi:10.1080/08927020902801548)
M. Moreau, D. Munteanu, J. L. Autran, F. Bellenger, J. Mitard, and M. Houssa, “Investigation of
Capacitance-Voltage Characteristics in Ge/High-κ MOS Devices”, Journal of Non-Crystalline Solids,
Vol. 355, 2009, pp. 1171-1175. (doi:10.1016/j.jnoncrysol.2009.01.056)
D. Munteanu, J. L. Autran, M. Moreau, and M. Houssa, “Electron Transport through High- κ Dielectric
Barriers: A Non-Equilibrium Green’s Function (NEGF) Study”, Journal of Non-Crystalline Solids, Vol.
355, 2009, pp. 1180-1184. (doi:10.1016/j.jnoncrysol.2009.03.006)
M. Moreau, D. Munteanu, and J. L. Autran, “Simulation of Gate Tunneling Current in Metal-InsulatorMetal Capacitor with Multi layer High-κ Dielectric Stack using the Non-equilibrium Green’s Function
Formalism”, Japanese Journal of Applied Physics, Vol. 48, 2009, p. 111409.
(doi:10.1143/JJAP.48.111409)
M. Moreau, D. Munteanu, and J. L. Autran, “Simulation Study of Short-Channel Effects and Quantum
Confinement in Double-Gate FinFET Devices with High-Mobility Materials”, Microelectronic
Engineering, Vol. 88, No. 4, 2011, pp. 366-369. (doi: 10.1016/j.mee.2010.08.026)
D. Munteanu, J. L. Autran, and M. Moreau, “Quantum Compact Model of Drain Current in
Independent Double-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors”, Japanese Journal of
Applied Physics, Vol. 50, 2011, p. 024301. (doi:10.1143/JJAP.50.024301)
D. Munteanu, M. Moreau, and J. L. Autran, “Effects of localized gate stack parasitic charge on
current-voltage characteristics of Double-Gate MOSFETs with high-permittivity dielectrics and Gechannel”, Journal of Non-Crystalline Solids, Vol. 357, 2011, pp. 1879-1883.
(doi:10.1016/j.jnoncrysol.2009.01.056)
W. Zhao, M. Moreau, E. Deng, Y. Zhang, J.-M. Portal, J.-O. Klein, M. Bocquet, H. Aziza, D. Deleruyelle,
C. Muller, D. Querlioz, N. Ben Romdhane, C. Chappert, D. Ravelosona, “Synchronous Non-Volatile
Logic Gate Design based on Resistive Switching Memories”, IEEE Transaction on Circuits and Systems
I, accepted for publication, 2013. ()
Liste de Communications 2009-2013 :
M. Moreau, D. Munteanu, J. L. Autran, F. Bellenger, J. Mitard, and M. Houssa, “Quantum Simulation
of C-V and I-V Characteristics in Ge and III-V Materials/High-κ MOS Devices”, Material Research
Society (MRS) 2009 Fall Meeting, November 30th - December 4th,Boston, MA, USA.
M. Moreau, D. Munteanu, J. L. Autran, F. Bellenger, J. Mitard, and M. Houssa, “Quantum Simulation
of C-V and I-V Characteristics in Ge and III-V Materials/High-κ MOS Devices”, in High-k Dielectrics on
Semiconductors with High Carrier Mobility (edited by P.D. Ye, M. Hong, W. Tsai, A. Dimoulas),
Materials Research Society Symposium Proceedings, Vol. 1194E, 2010, 1194-A02-02.
(doi:10.1557/PROC-1194-A02-02)
M. Moreau, D. Munteanu, J. L. Autran, “Simulation Study of Short-Channel Effects and Quantum
Confinement in Double-Gate FinFET Devices with High-Mobility Materials”, European-Material
Research Society (E-MRS) 2010 Spring Meeting, June 7th – 11th, 2010, Strasbourg, France.
D. Munteanu, M. Moreau, J. L. Autran, “Effects of gate stack parasitic charge on current-voltage
characteristics of High-κ/SiO2/Ge-channel Double-Gate MOSFETs”, 8th Symposium SiO2 Advanced
Dielectrics and Related Devices, June 21st - July 23rd, 2010, Varenna, Italy.
Y. Zhang, E.Y. Deng, J.O. Klein, D. Querlioz, D. Ravelosona, C. Chappert, W.S. Zhao, M. Moreau, J.M.
Portal, M. Bocquet, H. Aziza, D. Deleruyelle, C. Muller, “Synchronous Full-Adder based on
Complementary Resistive Switching Memory Cells”, IEEE 11th International New Circuits and Systems
Confererence, June 16th – 19th, 2013, Paris, France.
J.M. Portal, M. Moreau, M. Bocquet, H. Aziza, D. Deleruyelle, C. Muller, Y. Zhang, E. Deng, J.O. Klein,
D. Querlioz, D. Ravelosona, C. Chappert, W.S. Zhao, “Analytical Study of Complementary Memristive
Synchronous Logic Gates”, IEEE/ACM International Symposium on Nanoscale Architectures, July 15th
– 17th, 2013, New-York City, USA.
Participations GDR, plateformes-technologiques, autres … :
PICS CNRS IM2NP/IMEC (Belgique, 2007-2010), ANR P2N DIPMEM (2012-2015)
Collaborations (nationales et/ou internationales) avec d’autres laboratoires de Recherche :
CEA-LETI (Grenoble), IEF (Paris), LIRMM (Montpellier), STMicroelectronics (Crolles), CEALITEN (Grenoble)