EU CATRENE / ENIAC EDA Roadmap

Transcription

2010
EU CATRENE / ENIAC
EDA Roadmap
2008
Working Group DESIGN METHODS & TOOLS
Under Leadership of Livio Baldi, Numonyx
Ahmed A. Jerraya
CEA-LETI
[email protected]
Catrene/ENIAC RM June 2010 Ahmed Jerraya
© CEA 2008. Tous droits réservés.
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All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
1
Working Group
DESIGN METHODS & TOOLS
2008
STMicroelectronics
Infineon
NXP
Bosch
PoliTorino
CEA-LETI
IMEP-LAHC
Fzi-U.Tubingen
IMEC
IUNET
UCL
P.G.Rolandi
R.Pferdmenges
Peter Zegers
P. Van Staa
E. Macii
A. Jerraya
Ph. Ferrari
W. Rosenstiel
C. Martens
Rudy Lauwereins
E. Sangiorgi
D. Flandre, D. Bol
Numonyx
L.Baldi
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
[email protected],
David Bol [[email protected]]
[email protected]
2
Impact Factors
Design is the bridge between
technology and applications
 Impact on key applications: Design competence is the main
differentiating factor for high tech industry… Design efficiency is
a key element in containing development costs of new products
and supporting key European high tech sectors (automotive,
telecom)… Smart design is the key to energy saving in
2008
electronic systems.
 Opportunities: IP design and design services are a thriving
market for SME’s in Europe (more than 300 now)… More than
15,000 designers in Europe… Low entry barrier for SME’s in
design and tools.
3
Market Size
 Impact on European industry is
mainly through competitiveness
of semiconductor design.
 European systems/products e.g.
automotive, automation,
aviation/aerospace) need
innovative electronic solutions
for differentiation.
 Total investment in
semiconductor design in Europe
in 2008 is around 2.5 B€.
 Roughly
50000 designers active
2008
in Europe.
 Investment on Design Tools by
European semiconductor
industry (IDM and fabless) was
roughly 1 B$ in 2008 (25% of
R&D investment)
 Western Europe represents 20%
of the market.
Physical
21%
IP & tools
15%
PCB/MCM
13%
Services
9%
VHDL
42%
European EDA market 2007
Total value: 1.097 B$
4
Driving Forces
 Applications are becoming more complex in terms:

Number of devices
 Number of implemented functions
 Time to mass market is reducing.
 Design Technologies are the key enabling factor to meet the
challenge.
2008
Design Cost
Time to Market
5
Differentiated European Market
50
Market size [%]
40
30
Europe
World
20
10
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2008
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Complexity
A new scenario
2008
System in
Package
3D-SoC
System on
Chip
Covered by
big EDA
vendors
Standard
Logic
NEW
Analog
RF
Power
Sensors
Bios
Technology Heterogeneity
7
Planning European Research
ENIAC
SRA
Common pan-European
Strategic Research Agenda
Through FP7
Workprogramme
preparation
2008
FP7
Upstream
R&D
Direct control
through
industrial
committee
Definition of
CATRENE
White Book
Joint
EUREKA
Technology
CATRENE
Initiative
MEDEA+
Industry +
Transnational
Countries +
programs
EC
Through
national
platforms
National
National
programs
National
programs
programs
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CATRENE White Book
ANNEX 1: Design automation sub-work areas
1. Specification and validation
2. System architecture exploration
3. Hardware-dependent software
4. Mixed analog/digital and RF
5. Electronic design automation for MEMS
6. Verification, validation and test
7. Low-power design solutions
2008
8. Rapid system prototyping
9. Test development for SoC and SiP
10. Design for manufacturability
11. Reliability by design
12. Design methodologies/tools for fail-safe SoCs – comparable to self-adapting chips
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Grand Challenges in MASP
Design efficiency for functional complexity
•
•
•
•
•
•
•
Tools for Architecture Exploration and Optimization of Heterogeneous Systems
Behavioral models for high level design of heterogeneous functions.
Design environment for New Heterogeneous and Homogeneous Architectures and 3-D integration
Hardware-software partitioning and verification.
Tools for mixed analogue/digital/RF linked to system simulation, including SiP integration
Tools for package-IC co-design, multi-chip and 3-D integration, PCB-interfaces, Design
environment for constraint driven design for specific applications.
Deterministic verification methodologies/tools
Reliability and yield by design


2008




Electromagnetic Compatibility and Signal integrity
Modeling of reliability effects (aging, soft errors, electro-migration, Electrostatic Damage,
Electromagnetic coupling, temperature and hot spots, substrate noise)
Robust system design, including reconfigurability, redundancy and ECC
Yield optimization through statistical design, layout processing, yield-learning DFT
Advanced DFT, especially for analogue/mixed signal and System Level BIST
Verification driven design
Energy efficient design



Energy modelling and estimation at different abstraction levels for heterogeneous technologies
Dynamic and static energy management for heterogeneous systems
Thermal and variation-aware design under tight energy constraints
10
A Common Strategy
2008
Joint document:
Vision, Mission and Strategy
Differentiated Calls
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A strategic vision
 Design Technologies are a critical enabling factor for all
applications.
 The European trend towards More than Moore and
System in Package integration requires the development
of specific Design Technologies not supported by major
EDA vendors.
 New tools will require a broad European effort with a
strong participation of research centers and mediumlong term horizon.
2008
 Specific methodologies require a stronger involvement of
companies on specific application projects.
12
Innovation
for industry
2008
13

EU CATRENE / ENIAC EDA Roadmap

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