ESPADON - (CCT) du CNES

Transcription

ENVIRONMENT FOR SIGNAL PROCESSING
APPLICATIONS DEVELOPMENT AND PROTOTYPING
Brigitte SAGET, MBDA
Atelier CNES « Composants commerciaux pour l ’informatique embarquée », Toulouse, 12 Juin 2002
ESPADON objectives
*
Define an advanced development methodology and specify a
Design Environment to support this methodology
*
Select the commercial tools to be integrated in the ESPADON
Design Environment
*
Implement the ESPADON Design Environment with its selected
tools
*
Benchmark the ESPADON methodology and Design
Environment with Signal Processing Test Applications
*
Demonstrate the benefit in terms of development cost and
development time reduction.
Military systems development context
Billions of FF
YEARS
2000
Billions of ECUs
700
600
500
400
300
1990
100
USA
50
140
20
120
1980
1 GFlops/s
A few modes
10 GFlops/s
PROCESSING
POWER
100
FRANCE
80
10
60
UK
40
Multimodes
20
Extended Multimodes
NETHERLANDS
0
FUNCTIONS
1990
INCREASED
COMPLEXITY
SHRINKING
BUDGETS
INCREASED
COMPETITION
CHANGES IN
ELECTRONIC
INDUSTRY
(USA, WORLDWIDE)
DEVELOPMENT OF
NEW MILITARY
SYSTEMS
0
1995
Technology insertion concept
Performance
"log" scale
Conventional
Development
Method :
Retrofit
Retrofit
rs
yea
2
ry
eve
Final product
1rst Prototype
Programme Start
Final product
T end of development
2X
P: Expected level of performance of the final product ent :
em
rov
p
e Im
c
n
a
rm
rfo
e
Prototype
2nd Prototype
sP
c
i
on
ctr
Ele
:
AW
L
E’S
OR
O
M
Iterative
Development
Method :
Time
Virtual Prototyping & Technology Insertion
FUNCTIONAL DESIGN
CODE
FUNCTIONAL
SIMULATION
PERFORMANCE/
BEHAVIOURAL
SIMULATION
Models
HARDWARE / SOFTWARE ARCHITECTURAL DESIGN
Models
HARDWARE/SOFTWARE
COSIMULATION
NEW SOFTWARE
RE-USED SOFTWARE
AUTO-GEN CODE
FUNCTIONAL
REFERENCE MODEL
HARD/SOFT
CODEVELOPMENT
HARDWARE
VIRTUAL PROTOTYPE
Models
NEW HARDWARE
RE-USED HARDWARE
COTS
SOFTWARE
Technology insertion,
Manufacture,
Integration & Test
The ESPADON Methodology
Plan SP Development
From System Development
•
•
•
•
R
e
q
u
i
r
e
m
e
n
t
s
Risk driven development life cycle
« Model Year » approach
Reuse and capitalisation
Support for:
- Trace-ability
- cost performance trade off
From Previous Process
R
i
s
k
R
e
g
i
s
t
e
r
D
e
v
e
l
o
p
m
e
n
t
P
l
a
n
Specification
Functional Design
Architectural Design
Implementation
System Review
Development Plan
Requirements
To System Development
Risk Analysis
Definition
Development
Validation
Review
Risk Register
To Next/Previous Process
The ESPADON Methodology
Phase 1:
Analysis and Selection of the requirements
allocated to SP Subsystem
Plan SP Development
From System Development
From Previous Process
Requirements
Spiral Model Representation
Risk Analysis
Definition
Development
Validation
Risk Register
• Risk driven development life cycle
• « Model Year » approach
• Reuse and capitalisation
• Support for:
- Trace-ability
- Cost performance trade off
Phase 2:
Definition of SP Subsystem
INCREASING LEVEL OF REFINEMENT
SP production
Hardware/Software
description
D
Mapping
R Development
R
eExample
Specification
Plan of risk:
Software development
description
e
i
v
Refinement of
Example of risk:
q
s
e
Real time performance
architecture choice
u
Review
k
l
Computer
Example of risk:
i
o
Functional Design
architecture
Computing power
choice
r
R
p
Example
of
risk:
SP
Functional
definition
e
eGO/NO
m GO
SP algorithms, ...
m
g
e
To
Next/Previous
e
i
n
Architectural Design
Process
Functional
Simulation
n
s
t
modelling
t
t
Placement
Choice
of functions
validation
s
e
P
Development of
r
l Validation
Implementation
performance model
of performance model
a
Software/Hardware
Validation
development
ofnvirtual prototype
(synthesis)
Validation of
manufactured computer
Phase 4:
Validation of SP
Subsystem
System Review
To System Development
Production
Integration
Phase 3:
Development
of SP Subsystem
Tool List
Project Planning:
ARTEMIS - KUB Sistem SDN. BHD.
Requirements Analysis:
RTM - Marconi Systems Technology Inc.
RDD100 - Ascent Logic (US)
DOORS - Quality Systems Software Ltd.
Cost Estimation:
PRICE - Lockheed (US)
KNOWLEDGE - Software Productivity Research
Performance Simulation:
BONES - Cadence Design Systems Inc (US)
SES/WORKBENCH - SES (US)
OPNET - MIL 3 (US)
COSMOS - Omniview (US)
MODLINE - Simulog (Fr)
High Level Simulation:
SPW - Cadence Design Systems (US)
RIPPEN - Orincon (US)
SYSTEMVIEW - Elanex Inc (US)
GEDAE - Lockheed Martin ATL (US)
PTOLEMY - UCB (US)
MATLAB - The Math Works Inc (US)
MATLAB/SIMULINK - The Math Works Inc (US)
COSSAP - Synopsys Inc (US)
HP ESOF - HP
High Level Simulation (continued):
DSP STATION - Mentor (US)
DSP CANVAS - Angels Design System (US)
HYPERSIGNAL BLOCK DIAGRAM - Hyperception (US)
MUSTIG - Gresilog (Fr)
PEAKWARE - Matra Systemes et Information
Control Simulation/FSM:
STATEMATE- I-Logix Inc.
MATRIXX - Integrated Systems Inc.
SYNCCHART/ESTEREL - Simulog (Fr)
OBJECTGEODE - Verilog (Fr)
Co-design/co-simulation:
FELIX/VCC - Cadence Design Systems Inc (US)
EAGLEI - Synopsys (US)
Seamless - Mentor (US)
COWARE - CoWare N2C (US)
AREXSYS - Arexsys (Fr)
Configuration Management:
CLEARCASE - Rational (US)
RCS/CCS - Freeware
Miscellaneous:
02 - Ardent software (US)
OBJECTSTORE - Object Design (US)
VERSANT - Versant (US)
RATIONAL ROSE - Rational Software Corp.
Tools Selected - Rapid Prototyping
Configuration Mgmnt
(CVS, Clearcase)
EDE Framework
Requirements Analysis
(RDD100, DOORS)
COST ESTIMATION
(PRICE)
Matlab
Simulink/RTW
Ptolemy
GEDAE
External
Tools
• Algorithm
Prototyping
• Functional Design
• Architectural Design
• Implementation
(Rapid Prototyping)
Target- Porting Kit
VSIP
MPI-RT
Range of Target H/W
• Libraries
• Standards
Tools Selected - Virtual Prototyping
Functional Design/Simulation
e.g. Ptolemy/GEDAE
Current proposition
Process
Partitioning/Mapping
Processors
DSP
Libs
FPGA
Linking
Range of Target H/W
IP authoring tool
eg Handel C/ ART
Opt.
Libs
Planned Solution for Virtual Prototyping
Functional Simulation
Architecture
Characterisation
Data books, IP
System
Behaviour
Architecture
Definition
Mapping
Behavioural
Libraries
Performance
Simulation
Communication
Refinement
Software
Design
OS, drivers
& Legacy code
Architecture
Libraries
«C»
Links to Implementation
Co
Verification
ESPADON Platform
Integration
Hardware
Design
HDL
IP Libraries
System C,
VHDL, VERILOG
Results
*
Definition of a process and a methodology
•
addressing obsolescence and COTS insertion issues through rapid
and virtual prototyping, for Signal Processing applications
*
Overview of the required techniques and available
technologies and tools
*
Demonstration of resulting productivity gains through
representative radar & sonar benchmarks (adaptive
beamforming)
•
Demonstrated x1.4 to x 16 Productivity (V0)
•
Benchmark of the process, estimated productivity of x7.5 (V1)
ESPADON Demonstrated Benefits
*
*
*
*
Reduction of development cost and time
•
productivity improvement : code generation
•
reduction of errors : early validation by simulation
•
dealing with late changes: delaying the need for hardware prototypes
Reduction of programme risks
•
risk driven process
•
incremental approach : simulation and prototyping
Mitigation of obsolescence problems / Retrofit
•
technology insertion through rapid prototyping
•
process based on a functional model and code generation facilitate the porting of
an application on different architectures : PPC => FPGA
Facilitation of collaborative developments
•
complexity management
•
reuse libraries
•
open, modular architectures and standards

ESPADON - (CCT) du CNES

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