Analog-‐to

Analog-­‐to-­‐Digital Measurements and digital circuits G. De Lentdecker and K. Hanson ULB PHYS-­‐F-­‐314 Shannon/Nyquist and Fourier QUELQUES MOTS SÛR SAMPLING THEORY 2 DécomposiKon Harmonique des Signaux Observez que l’onde carré est décomposable en la sommaKon des sinus. La reconstrucKon est montrée à droit pour 1, 2, 8, et 32 termes dans la sommaKon SQR(t) =
fper
∞
�
sin(2πf (2k − 1)t)
(1) (2k − 1)
k=1
1
N’importe foncKon périodique sûr l’intervalle [-­‐π,π] peut être représenté par une série illimitée des sinus et cosinus – la série de Fourier Fundamental
1st Harmonic
8th Harmonic
32nd Harmonic
0.5
∞
a0 �
=
+
[an cos(nx) + bn sin(nx)]
2
n=1
(2.a) �
1 π
an =
fper (x) cos(nx)dx
π −π
� π
1
bn =
fper (x) sin(nx)dx
π −π
(2.b) (2.c) Amplitude (a.u.)
Plus souvent elle est exprimé par la série complexe +∞
�
fper (x) =
cn einx
� π n=−∞
1
cn =
fper (x)e−inx dx
2π −π
0
-0.5
-1
0
0.2
0.4
0.6
0.8
1
Time (a.u.)
1.2
1.4
1.6
1.8
2
(3.a) (3.b) Ainsi, on a deux choix pour décrire une foncKon: soit en temps (la variable dépendant x est typiquement liée à temps) , soit en fréquence. Dans le premier cas, on garde les échanKllons de fper et dans le deuxième on a les coefficients cn (ou an et bn). 3 TransformaKon de Fourier L’uKlité de le précédent devient claire quand on considère un approximaKon à la foncKon fper qu’est vue typiquement dans les problèmes réelles: la foncKon peut représenter un signal, pour exemple, la tension en sorKe d’un microphone, variant en temps. Souvent on échanKllonne le signal aux intervalles réguliers: 2πk
fper (x) → fper (xk ) ≡ fk , xk =
, k = 0, 1, ..., N − 1
N
Maintenant, réécrivez Eq. (3.b) dans la forme discrète: cn
=
N −1
1 �
2π
fk e−2πikn/N ∆x, ∆x =
2π
N
k=0
=
N −1
1 �
fk e−2πikn/N
N
k=0
Notez, qu’il y a seulement N valeurs uniques pour cn en remplaçant n  n + N on peut le montrer. Ainsi, un foncKon f, échanKllonné régulièrement N fois dans une intervalle [-­‐π, π] a une transformaKon dans l’espace fréquenKelle déterminé par N coefficients complexes. Cefe DFT (Discrete Fourier Transform) est très populaire due à l’algorithme FFT (Fast Fourier Transform). 4 Sampling Theorem of Nyquist and Shannon A surprising theorem from Shannon and Nyquist states that in fact you can record everything needed to completely reconstruct a funcKon if that funcKon is bandwidth limited to some fC and as long as you sample faster than 2fC called someKmes the Nyquist frequency, someKmes the cri3cal frequency. Formally, the funcKon f(t) is reconstructed from its samples fn using the sinc funcKon: +∞
�
sin[2πfc (t − n∆)]
f (t) = ∆
hn
π(t − n∆)
n=−∞
However, in pracKce, most ohen the sinc funcKons are simply approximated by rectangles. Moreover, in the real world it is impossible to sample for an infinite amount of Kme and therefore the signal can never be perfectly band-­‐limited. These approximaKons are normally so close to the ideal case that their effects are miniscule. ViolaKon of the Nyquist-­‐Shannon rule causes an effect known as aliasing whereby the frequencies above the Nyquist frequency “wrap-­‐around” and are mixed into the lower frequencies causing distorKon errors during reconstrucKon. 5 General Remarks about A/D and D/A •  You would never construct for yourself a converter unit. These days 1000’s are cheaply available to suit many specific applicaKons – see Farnell catalog, for example. •  The precision of the converter is a criKcal parameter. If you have a 10-­‐bit ADC then that means that you can sample 1024 different values (210). AlternaKvely, if the reference voltage is 5 V that means that the digital output would only be capable of encoding 4.88 mV steps. •  In view of the remarks on Nyquist sampling above, ohen an ADC system contains a LPF in front of the converter. Since no LPF is a ‘brick wall’ some amount of oversampling is ohen used to reduce signal aliasing effects. 6 DIGITAL-­‐TO-­‐ANALOG CONVERSION 7 R-­‐2R Ladder The general idea behind digital-­‐to-­‐analog conversion (DAC) uses an op-­‐amp current summing juncKon – where the currents are controlled by a digitally encoded binary number. A very popular design is the so-­‐called R-­‐2R ladder which uses a configuraKon of just two resistor values, one exactly twice the resistance of the other. The circuit for a hypotheKcal 4-­‐bit DAC is shown below. The switches J1-­‐J4 are CMOS muxers which are controlled by perhaps a set of flip-­‐flops holding the binary number. Switch J1 is the MSB and switch J4 is the LSB. Since either posiKon of the switches results in the resistors seeing some sort of ground (either real or virtual if they are connected to the op-­‐amp) it is possible to analyze this circuit by simply imagining the ladder resistors grounded at each point. Note that the output voltage will be related to the reference voltage, in this diagram 10 V, and will be: Vout
� n �
= Vref N
2
Where n is the binary digital input and N is the number of bits of the DAC. In general then the output voltage will never exactly equal the reference voltage even when it is at “full scale.” 8 Comparators ANALOG-­‐TO-­‐DIGITAL CONVERSION 9 Sample and Hold It is important to make sure that the signal is stable during the process of conversion otherwise bad things will happen. A circuit called a “sample-­‐and-­‐hold” or S/H is ohen needed in order to enforce this condiKon. It takes as input an analog signal at “In” and a digital input “Hold” which if high will close the FET Q1 and effecKvely isolate the voltage level on C1 as it is buffered on the output by the JFET buffer U1B. Ohen the S/H circuitry is included on the ADC. 10 Comparateurs Un comparateur (parfois discriminateur) dira si une tension est supérieur ou inferieur d’un seuil, donc il agit comme un 1-­‐bit ADC (analog-­‐to-­‐digital converter, CAN en français pour converKsseur analogique numérique). C ’est possible de rencontre les problèmes en uKlisant un comparateur avec les signaux lentes ou en présence d’un bruit important. Comme est dépeint dans la figure, le circuit simple ne change pas la sorKe aussitôt quand l’entrée travers le seuil (5 V): il y a au moins 2 transiKons à cause du bruit – le seuil est traversé plusieurs fois. En ajoutant le feedback posiKf dans ce « Schmidt Trigger » circuit, c’est possible de changer le seuil en foncKon d’état de la sorKe. 11 Parallel Encoder The parallel encoder operates by presenKng the input voltage to mulKple (in pracKce 10-­‐bit parallel flash ADCs with consequent eyeball-­‐
popping price tags and power dissipaKon figures. Nevertheless, it is the fastest conversion technique. Each comparator below threshold will have a ‘1’ output and those above threshold will have a ‘0’ output. The ‘148 priority encoder will output the address of the highest ‘1’ on input. There is a version of the flash encoder called a pipelined flash which converts in several stages, for example the upper 4 bits and the lower 4 bits. This greatly reduces the silicon needed at a slight expense of speed. These are the most popular high-­‐speed converters today operaKng at speeds in excess of 100 MSPS and up to 16-­‐bit precision (10-­‐, 12-­‐ and 14-­‐bit are also popular). 12 Successive ApproximaKon Method Lower-­‐speed ADCs (up to a few MHz) ohen uKlize the method of successive approximaKon. An internal register called the SAR or successive approximaKon register uses a DAC and a comparator, both also internal to the ADC to compare its guesses to the true value of the input voltage: 1.  The sequence starts by se•ng the MSB of the SAR. 2.  If the input is higher than the “guess” voltage then the set bit is kept. Otherwise it is reset to zero. 3.  The control logic then moves to the next lower bit and repeats the process. 4.  Aher all bits have been processed, the digiKzer signals that it has finished and presents the digital data stream, either in parallel or in serial. From Horowitz & Hill The Art of Electronics 2nd Ed. 13 TIME-­‐TO-­‐DIGITAL CONVERSION 14 Analog TDC The analog method involves the charging of a capacitor with a known current (i.e. current source) for a Kme interval bounded by two let’s suppose digital pulses TRIGA and TRIGB. The top-­‐level of the circuit is shown at leh. The Coincidence block processes the input signals and passes the triggers to the TimeIntegrator blocks’ Start inputs which should start the current integraKon process. How to stop them? The Coincidence must also contain logic to generate a COMMON STOP signal which happens a set Kme aher BOTH triggers have fired. There is also a COMMON START TDC which starts the integraKon on a common signal and stops each integrator on TRIGA and TRIGB. The integrator includes an SRFF which gates switch Q5 which can either pass the current from the current source Q1 (about 3 mA) or will block. When the switch is open capacitor C1 charges at a rate dV/dt = I / C = 30,000 V/sec. It will have a full scale of approximately several 100’s of µsec. The TI output will be held as long as CLR is not asserted and can be digiKzed by an ADC. What Kme resoluKon would this circuit give you if you used a 12-­‐bit ADC with a full-­‐scale Vref of 5V? 15