Annual Report 2004

Annual Report 2004
JAHRESBERICHT 2004 | INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
Impressum/Imprint
Herausgeber/Publisher
IHP GmbH – Innovations for High Performance Microelectronics/ Institut für innovative Mikroelektronik
Postadresse/Postbox
Postfach 1466/ Postbox 1466
15204 Frankfurt (Oder)
Deutschland/Germany
Besucheradresse/Address for visitors
Im Technologiepark 25
15236 Frankfurt (Oder)
Deutschland/ Germany
Telefon / Phone +49.335.56 25 0
Telefax / Fax
+49.335.56 25 300
E-Mail [email protected]
Internet www.ihp-microelectronics.com
Redaktion /Editors
Dr. Wolfgang Kissinger/ Heidrun Förster
Gesamtherstellung/Production in design and layout
Publishers an der Oder
Ferdinandstraße 15
15230 Frankfurt (Oder)
Telefon/ Phone +49.335.41 45 90
Telefax / Fax
+49.335.41 45 923
E-Mail [email protected]
Internet www.publishers-oder.de
Bildnachweise/Photocredits
IHP GmbH; Winfried Mausolf; Publishers an der Oder; Timo Röder
Soweit nicht anders vermerkt, liegt das Copyright für die selbst erstellten Texte und Abbildungen von IHPMitarbeitern allein bei der IHP GmbH.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Annual Report 2004
JAHRESBERICHT 2004 | INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
Vorwor t
Foreword
Das IHP konzentriert sich auf die Erforschung und Entwicklung innovativer Lösungen für die drahtlose und
Breitbandkommunikation. Als Leibniz-Institut verfolgt es
langfristige Zielstellungen und verbindet dabei Grundlagenforschung mit angewandter Forschung. Es versteht
sich als ein europäisches Forschungs- und Innovationszentrum, dass grundlegende Ergebnisse bis zu industriell
relevanten Prototypen weiterführt.
Das vertikale Forschungskonzept des IHP beinhaltet
die Entwicklung neuer Lösungen unter Einbeziehung
mehrerer Ebenen der Wertschöpfung. Dabei setzt das
Institut gezielt seine aufeinander abgestimmten Kompetenzen im System Design, dem Design von Hochfrequenzschaltungen, der Halbleitertechnologie sowie
der Materialforschung für die Mikroelektronik ein. Eine
weitere wichtige Besonderheit ist die Pilotlinie mit ihren sehr leistungsfähigen BiCMOS-Technologien. Sie
ermöglicht dem IHP und seinen Partnern, Prototypen
mit hervorragenden Leistungsparametern und mit integrierten zusätzlichen Funktionalitäten zu realisieren.
Im vergangenen Jahr konnte die Zusammenarbeit des
Institutes mit der Industrie, die Teilnahme an nationalen und europäischen Verbundprojekten sowie die Kooperation mit den regionalen Hochschulen in Cottbus,
Wildau und Berlin wesentlich ausgebaut werden. Ebenso wuchs die Anzahl von Firmen, Forschungseinrichtungen und Hochschulen, die Technologien des IHP über
den MPW und Prototyping Service für ihre Forschungsund Entwicklungsarbeiten nutzen.
Mit dem Ausbau dieser Kooperationen ist es dem IHP
gelungen, die für seine Forschungsprogramme erforderlichen Drittmittel einzuwerben. Von großer Bedeutung für die längerfristige Entwicklung des Institutes
ist die im Jahr 2004 begonnene Modernisierung seiner
Ausrüstungsbasis mit Hilfe des Europäischen Fonds für
regionale Entwicklung.
Die in diesem Bericht dargestellten internationalen
Spitzenleistungen wurden durch die engagierte Arbeit
unserer Mitarbeiterinnen und Mitarbeiter möglich. Ihnen gilt unser besonderer Dank. Ebenso danken wir der
Brandenburgischen Landesregierung und der Bundesregierung für ihre außerordentliche Unterstützung.
Frankfurt (Oder), Mai 2005
Wolfgang Mehr
Wiss.-Techn. Geschäftsführer
2
Prof. Dr. Wolfgang Mehr
The IHP concentrates on
the research and development of solutions for wireless and broadband communication. As a Leibniz
Institute it pursues longterm goals and in doing so
connects basic research
with applied research. It
sees itself as a European
research and innovation
center which develops basic results into prototypes
relevant for industry.
IHP’s vertical research concept entails the development
of new solutions considering several levels of the valueadded chain. To this end the institute specifically aims at
utilizing its harmonized competencies in system design,
the design of RF circuits, semiconductor technology as
well as materials research for microelectronics. Another
important feature is the pilot line with its very high performance BiCMOS technologies, which enables the IHP to
realize prototypes with excellent performance parameters and additionally integrated functionalities.
Last year the institute managed to intensify its cooperation with industry and regional universities in Cottbus, Wildau and Berlin, and to take part in national and
European joint projects. At the same time there was
a growth in the number of companies, research centers and universities using IHP’s technologies via MPW
and Prototyping Service for their research and development projects.
By intensifying such cooperation, the IHP succeeded in
acquiring the third-party funding needed for its research
programs. What is of particular significance for the longterm development of the Institute is the modernization
of its basic equipment, which began in 2004 with the
help of the European Regional Development Fund.
The international first-rate performance presented in
this report is attributable to the dedication of IHP’s
employees, which is why we would like to pay them our
particular thanks. We would equally like to thank the
regional government of Brandenburg and the federal
government for their exceptional support.
Manfred Stöcker
Admin. Geschäftsführer
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Inhaltsverzeichnis
Seite
Contents
Page
Vorwort/Foreword
2
Aufsichtsrat/Supervisory Board
4
Wissenschaftlicher Beirat/Scientific Advisory Board
5
Das IHP auf einen Blick/IHP in a Nutshell
6
Das Jahr 2004/Update 2004
8
Angebote und Leistungen/Deliverables and Services
16
Forschung des IHP/IHP’s Research
24
Ausgewählte Projekte/Selected Projects
28
Drahtloses Internet/ Wireless Internet
29
Technologieplattform/Technology Platform
38
Materialien für die Mikroelektronik/Materials
for Microelectronics
50
Gemeinsames Labor IHP/BTU – IHP/BTU Joint Lab
58
Konferenzen und Workshops/Conferences and
Workshops
62
Zusammenarbeit und Partner/Collaborators and
Partners
66
Gastwissenschaftler und Seminare/Guest Scientists
and Seminars
70
Publikationen/Publications
74
Nachdrucke ausgewählter Publikationen/
Reprints of Selected Publications
75
Erschienene Publikationen/
Published Papers
124
Eingeladene Vorträge/Invited Presentations
134
Vorträge/Presentations
136
Berichte/Reports
143
Monografien/Monographs
145
Patente/Patents
146
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
3
Aufsichtsrat
Super visory Board
Aufsichtsrat
Supervisory Board
Konstanze Pistor
Konstanze Pistor
Vorsitzende
Ministerium für Wissenschaft, Forschung und Kultur
Land Brandenburg
Chair
Ministry of Science, Research and Culture
State of Brandenburg
MinDirig Dr. Wolf-Dieter Lukas
Dr. Wolf-Dieter Lukas
Stellvertretender Vorsitzender
Bundesministerium für Bildung und Forschung
Deputy
Federal Ministry of Education and Research
Prof. Dr. Helmut Gabriel
Prof. Helmut Gabriel
Freie Universität Berlin
Freie Universität Berlin
Dr. Harald Richter
Dr. Harald Richter
IHP
IHP
Prof. Dr. Ernst Sigmund
Prof. Ernst Sigmund
Brandenburgische Technische Universität Cottbus
Technical University of Brandenburg, Cottbus
Dr. Wolfgang Winkler
Dr. Wolfgang Winkler
IHP
IHP
MinR Gerhard Wittmer
Gerhard Wittmer
Ministerium der Finanzen
Land Brandenburg
Ministry of Finance
State of Brandenburg
Bis 30. November 2004
Until November 30, 2004
Staatssekretär Dr. Christoph Helm
Undersecretary of State Dr. Christoph Helm
Vorsitzender
Ministerium für Wissenschaft, Forschung und Kultur
Land Brandenburg
Chair
Ministry of Science, Research and Culture
State of Brandenburg
MinDir Dr. Peter Krause
Dr. Peter Krause
Stellvertretender Vorsitzender
Bundesministerium für Bildung und Forschung
Deputy
Federal Ministry of Education and Research
4
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Wissenschaf tlicher
Beirat
Scientific Advisory
Board
Wissenschaftlicher Beirat
Scientific Advisory Board
Prof. Dr. Hermann G. Grimmeiss
Prof. Hermann G. Grimmeiss
Vorsitzender
Department of Solid State Physics
Lund University, Schweden
Chair
Department of Solid State Physics
Lund University, Sweden
Dr. Jürgen Arndt
Dr. Jürgen Arndt
Stellvertretender Vorsitzender
ATMEL Germany GmbH, Heilbronn
Deputy
ATMEL Germany GmbH, Heilbronn
Prof. Dr. Ignaz Eisele
Prof. Ignaz Eisele
Fakultät für Elektrotechnik und Informationstechnik
Universität der Bundeswehr München
Department of Electrical Engineering and Information
Technology, University of the Bundeswehr, Munich
Prof. Dr. Christian Enz
Prof. Christian Enz
CSEM SA, Neuchatel, Schweiz
CSEM SA, Neuchatel, Switzerland
Prof. Dr. Ulrich Rohde
Prof. Ulrich Rohde
Synergy Microwave Corporation, USA
Synergy Microwave Corporation, USA
Dr. Josef Winnerl
Dr. Josef Winnerl
Infineon Technologies AG, München
Infineon Technologies AG, Munich
Prof. Dr. Günter Zimmer
Prof. Günter Zimmer
Fraunhofer IMS, Duisburg
Fraunhofer IMS, Duisburg
Leitung
Management
Prof. Dr. Wolfgang Mehr
Prof. Wolfgang Mehr
Wissenschaftlich-Technischer Geschäftsführer
Director
Manfred Stöcker
Manfred Stöcker
Administrativer Geschäftsführer
Administrative Director
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
5
Das IHP auf einen Blick
IHP in a Nutshell
Das IHP auf einen Blick
IHP in a Nutshell
Das Institut
The Institute
-
Gegründet 1983; 1991 Neugründung aus einem
früheren Akademieinstitut mit langjähriger Erfahrung in der Mikroelektronik auf Silizium-Basis
-
Founded in 1983; Re-established in 1993 as a successor institution to the former institute of the
East German Academy with extensive experience
in silicon microelectronics
-
ca. 200 Mitarbeiter aus 16 Ländern
-
200 employees from 16 countries
-
Mitglied der Leibniz-Gemeinschaft
-
Member of the Leibniz Association
Aufgabe
Mission
-
Wirkung als Europäisches Forschungs- und Innovationszentrum für drahtlose Kommunikationstechnologien
-
To act as a European Research- and Innovation
Center for wireless communication technologies
-
Stärkung der Wettbewerbsfähigkeit der deutschen
und europäischen Mikroelektronik- und Kommunikationsforschung
-
To strengthen the competitive position of the German and European microelectronic and communication research
-
Erhöhung der Attraktivität der Region als Hochtechnologiestandort
-
To enhance the attractiveness of the region as a
location for high technology
Strategie
Strategy
-
Wertschöpfung durch Innovation
-
To create value through innovation
-
Konzentration auf drahtlose und Breitbandkommunikation
-
To focus on solutions for wireless and broadband
communications
-
Entwicklung zukunftsorientierter Technologien,
Schaltkreise und Systeme bis zu Prototypen
-
Development of forward-looking technologies, circuits and systems up to prototypes
-
Strategische Partnerschaften
-
Strategic partnerships
Infrastruktur
Facilities
-
-
Vollständige Innovations-Kette vom Material bis zu
Systemen, einschließlich Pilotlinie mit 0,25 (0,13)-µmBiCMOS-Technologien
Complete innovation chain from materials to systems,
including a pilot line with 0.25 (0.13) µm BiCMOS
technologies
Kompetenzen
Competencies
-
Systeme für die drahtlose Kommunikation
-
Systems for wireless communication
-
HF-Schaltkreisentwurf
-
RF circuit design
-
Erweiterung von Silizium-CMOS-Technologien für
neue Funktionen
-
Extension of silicon CMOS technologies for new
functionalities
-
Materialien für die Mikroelektronik-Technologie
-
Materials for microelectronic technology
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
7
Das Jahr 2004
Update 2004
Das Jahr 2004
Update 2004
Im Jahr 2004 wurde die Forschungsarbeit des IHP entsprechend der erarbeiteten Strategie in den drei Forschungsprogrammen „Drahtloses Internet“, „Technologieplattform“ und „Materialien für die Mikroelektronik“
erfolgreich weitergeführt.
In the year 2004 the research of the IHP was continued according to the designed strategy successfully in the three research programs ”Wireless Internet“,
”Technology Platform“ and ”Materials for Microelectronics“.
Spitzenleistungen wie z.B. eine sehr leistungsstarke
komplementäre BiCMOS-Technologie und Schlüsselkomponenten für 60-GHz-Anwendungen fanden bereits starke internationale Beachtung und zeigen das
Potential des IHP.
Top results such as a very high performance complementary BiCMOS technology and key components for
60 GHz applications already received strong international attention and show the potential of the IHP.
Im Jahr 2004 gelang in allen Programmen eine Verbesserung der Kooperation sowie der nationalen und
internationalen Vernetzung der Forschung.
In 2004 an improvement in cooperation as well as the
national and international networking of the research
was noted in all the programs.
Von besonderem Wert ist das große Interesse der Industrie an den Arbeiten des IHP. Davon zeugen die
2004 eingeworbenen 5,1 Mio. Euro Drittmittel mit einem Industrieanteil von etwa 50% ebenso wie zahlreiche Arbeitsbesuche von Industrievertretern am IHP
sowie von IHP-Mitarbeitern bei der Industrie.
The particular interest of the industry in IHP‘s research
is from special value. This is refl ected in the 5.1 million
euros in third-party funding with an industrial portion
of approximately 50% obtained in 2004, as well as the
numerous visits to the IHP made by representatives of
the industry and the visits made by IHP staff to industrial companies.
Ausser durch zahlreiche Anwender aus Universitäten
und Forschungseinrichtungen wird der Multiprojekt Wafer (MPW) und Prototyping Service des IHP ebenfalls
von einer großen Anzahl Firmen für deren Forschungen
und Entwicklungen genutzt.
In addition to many users from universities and research institutes, the IHP Multi-Project Wafer (MPW)
and Prototyping Service is also being used by an large number of companies for their research and development.
Im Jahr 2004 arbeitete das IHP in mehreren nationalen
Verbundprojekten, so z.B. BASUMA, Wireless InternetAd Hoc, Wireless Internet-Zellular, Mobile Internet Business, WIGWAM, KOKON und SOBSI.
In 2004, the IHP worked on a number of national cooperative projects, for instance BASUMA, Wireless
Internet-Ad Hoc, Wireless Internet-Zellular, Mobile
Internet Business, WIGWAM, KOKON and SOBSI.
Innerhalb des 6. Rahmenprogrammes der EU ist das
IHP in den Projekten PULSERS und WINDECT tätig.
The IHP is working on the projects PULSERS and WINDECT within the EU’s Sixth Framework Programme.
Die Kooperation mit Hochschulen, insbesondere im Land
Brandenburg und in Berlin, wurde deutlich erweitert:
Cooperation with universities, especially in the states
of Berlin and Brandenburg, was expanded significantly:
Der Ausbau eines gemeinsamen Kompetenzzentrums für
Halbleitermaterialien und -technologien im Rahmen des
IHP/BTU Joint Lab wird auch in seiner zweiten Phase als
Forschungsprojekt im Rahmen des Hochschul- und Wissenschaftsprogramms gefördert. Die Forschungsinhalte
der Kooperation mit der BTU wurden 2004 neu strukturiert und mit den Forschungszielen des IHP abgeglichen.
Mit der TFH Wildau wurde die Kooperation in Forschung
und Lehre weiter ausgebaut. Eine Kooperationsvereinbarung mit der TU Berlin ist in Vorbereitung.
The expansion of a joint competence center for semiconductor materials and technologies in the framework
of the IHP/BTU Joint Lab will also be subsidized in its
second phase as a research project as part of the University and Science Program. The contents of the research cooperations with the BTU were restructured in
2004 and attuned to the IHP research objectives. The
cooperation in research and teachings was intensified
with the TFH Wildau. A cooperation agreement is being
prepared with the TU Berlin.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
9
Das Jahr 2004
Update 2004
An diesen Hochschulen halten IHP-Mitarbeiter Vorlesungen und betreuen Diplomanden bzw. Doktoranden.
IHP staff members hold lectures and advise students
and graduate students at these universities.
Eine wissenschaftliche Kooperation mit der EuropaUniversität Viadrina wurde mit dem Projekt „Mobile
Internet Business“ begonnen.
A scientific cooperation with the European University
Viadrina was initiated with the ”Mobile Internet Business“ project.
Das IHP war im Jahr 2004 aktiv an der Organisation
von zehn internationalen Tagungen auf seinen Arbeitsgebieten beteiligt, von denen drei in Frankfurt (Oder)
stattfanden.
In 2004, the IHP participated in the organization of 10
international conferences in its fields. Three of these
were held in Frankfurt (Oder).
Durch Mittel des EFRE-Strukturfonds ist es dem IHP
möglich, die technologische Ausrüstung, die erforderlichen Testsysteme und die Entwurfssoftware für das
0,13-µm-Strukturniveau aufzubauen. Mit der Realisierung dieser Investitionen wurde begonnen.
With funding from the EU Regional Development Fund,
it has been possible for the IHP to set up the technological equipment, the necessary testing systems and
the design software for the 0.13 µm structure level.
The realization of this investment has been initiated.
Zur Schaffung und zum Erhalt von Arbeitsplätzen in
der Region gibt es mehrere Aktivitäten zur Vorbereitung von Ausgründungen aus dem IHP und zur Unterstützung von Ansiedlungsplänen für MikroelektronikFirmen.
To create and maintain jobs in the region there are a
number of activities being prepared for spin-offs from
the IHP and to support the settlement activities for
microelectronics companies.
Wissenschaftliche Ergebnisse
Scientific Results
Drahtloses Internet: Systeme und Anwendungen
Wireless Internet: Systems and Applications
Die erfolgreiche Einwerbung von Drittmitteln ermöglichte ein deutliches personelles Wachstum in diesem
Forschungsprogramm. Im Rahmen der existierenden
Teilprogramme wurden inhaltliche Erweiterungen vorgenommen, so z.B. wurden die Arbeiten zu Low Power
durch Sensornetze und Anwendungen und die Arbeiten
zu High-Performance Systemen in Richtung Radar und
Satellitenkommunikation erweitert.
The success in obtaining third-party funding allowed
for significant growth in personnel in this research program. In the framework of the existing sub-program
expansions in the content were made, for instance,
the work on low power was expanded by sensor networks and applications, the work on high-performance
systems was expanded in the direction of radar and
satellite communication.
Beispiele für Ergebnisse im Jahr 2004 sind:
Examples of results in 2004 were:
1. Erarbeitung integrierter Lösungen für Systeme zur
drahtlosen Kommunikation mit hohen Datenraten.
Durch das Projekt 5-GHz-WLAN Modems wurden im
Herbst 2004 erste Design-Umgebungen (Link-Emulator) für Applikationsentwicklungen bereitgestellt.
Für die 60 GHz / 1 Gbps WLAN Lösung sind alle
HF-Komponenten entwickelt und erste Prototypen
verfügbar. Hier ist insbesondere die PLL (Phase
Locked Loop) hervorzuheben, die als weltweit erste
SiGe-PLL für 60 GHz gilt.
1. Development of integrated solutions for systems
for wireless communication with high data rates.
In the autumn of 2004, initial design environments
(link emulator) for application developments were
provided by the 5 GHz WLAN modems project.
All the RF components and initial prototypes were
developed for the 60 GHz/1 Gbps WLAN solution.
The PLL (Phase Locked Loop) deserves special
mention in this regard; it is the first SiGe PLL for
60 GHz in the world.
10
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Das Jahr 2004
Update 2004
2. Arbeiten zu Radarsensoren.
Für Radarsensoren wurden erste aktive und passive Mischer präpariert. Die Arbeiten zu 78 GHzSensoren werden im Rahmen des Projektes KOKON
weitergeführt. Hier sind erste sehr gute Ergebnisse bei LNA (Low Noise Amplifier) und VCO (Voltage
Controlled Oscillator) erzielt worden.
2. Work with radar sensors.
The fi rst active and passive mixers were prepared
for radar sensors, the work on 78 GHz sensors will
be continued within the framework of the KOKON
project. Here, very good initial results have been
obtained in LNA (Low Noise Amplifier) and VCO
(Voltage Controlled Oscillator).
3. Entwicklung von Middleware für innovative Anwendungen der drahtlosen Kommunikation.
Die Konzepte zur Security und Privacy wurden fertiggestellt und erfolgreich getestet. EncryptionProzessoren wurden erfolgreich gefertigt und getestet.
3. Development of middleware for innovative applications in wireless communication.
The concepts for security and privacy were completed and successfully tested. Encryption processors were successfully produced and tested.
4. Erarbeitung integrierter Lösungen für die Leistungsverstärkung bei hohen Frequenzen.
Integrierte Leistungsverstärker mit LDMOS erlauben den Einsatz sowohl für WLANS als auch für
Bluetooth ohne externe Bauelemente, was dem
Nutzer einen deutlichen Wettbewerbsvorteil bietet.
4. Development of integrated solutions for amplification in high frequencies.
Integrated amplifiers with LDMOS can be used in
both WLANS as well as for Bluetooth without external components, which allows users a significant
competitive advantage.
5. Erarbeitung eines integrierten Wireless Bus Systems für medizinische Anwendungen.
Erste Ergebnisse im Projekt BASUMA wurden mit
der Realisierung der MAC (Medium-Access-Control) -Protokolle und des Basisband-Transmitters
erzielt. Eine Zusammenarbeit mit der BTU Cottbus
im Bereich der Betriebssysteme soll ein neues
Basissystem für mobile Sensoren realisieren.
5. Development of an integrated wireless bus system
for medical applications.
Initial results in the BASUMA project were attained
with the realization of the MAC (Medium Access
Control) protocols and the baseband transmitter.
Cooperation with the BTU Cottbus in the area of
operating systems will develop a new base system
for mobile sensors.
6. Im Projekt UWB wurden alle Basiskomponenten für
ein pulsbasiertes UWB-System realisiert. Die Anwendung soll im Projekt BASUMA erfolgen.
6. In the UWB project all the basic components for a
pulse-based UWB system were realized. The application will be made in the BASUMA project.
7. Es wurden Prozessor-Bibliotheken für verschiedene Projekte mit den lizenzfreien Prozessoren ASPIDA und LEON-2 realisiert. Während der Prozessor
ASPIDA völlig asynchron ist, handelt es sich beim
LEON um einen 32-Bit-RISC Prozessor.
7. Processor libraries for various projects with the
license-free processors ASPIDA and LEON-2 were
realized. While the processor ASPIDA is completely
asynchronous, LEON is a 32-Bit RISC processor.
8. Neu wurde in 2004 mit Arbeiten zu schnellen Analog/Digital-Wandlern begonnen.
8. New in 2004 was the commencement of work on
fast analog/digital converters.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
11
Das Jahr 2004
Update 2004
Technologieplattform für drahtlose und Breitbandkommunikation
Technology Platform for Wireless and Broadband
Die vorhandenen 0,25-µm-BiCMOS-Technologien wurden im Jahr 2004 weiterentwickelt und durch zusätzliche Module mit neuen Funktionen erweitert.
Mit der ausrüstungs- und technologieseitigen Vorbereitung der 0,13-µm-BiCMOS-Technologie wurde begonnen. Der Vorbereitung dieser Technologie dienten auch
Entwicklungen neuer Konzepte für schnelle HBTs.
The 0.25 µm BiCMOS technologies were further developed in 2004 and expanded by new functions with
additional modules.
Preparations for the equipment and technology of the
0.13 µm BiCMOS technology were begun. The preparation of this technology also serves the development
of new concepts for fast HBTs.
Beispiele für Ergebnisse im Jahr 2004 sind:
Examples of results in 2004 were:
1. Integration extrem schneller, komplementärer Hetero-Bipolartransistoren.
Es gelang erneut, Weltrekord-Werte für die Gatterverzögerungszeiten siliziumbasierter Transistoren
zu erreichen. So wurden für npn-Transistoren mit
maximalen Transit- bzw. Schwingfrequenzen von
f T/f max = 300/250 GHz und Durchbruchspannungen
von BVCE0 = 1,8 V Gatterverzögerungen von 3,2 ps
erreicht. Für pnp-Transistoren wurde bei f T/f max =
135/140 GHz und BVCE0 = 2,5 V mit 5,9 ps ebenfalls ein neuer Weltrekord erzielt.
Ausserdem wurde eine Lösung zur Verbindung von
Hochgeschwindigkeits-HBTs und Dünnschicht-SOISubstraten (Silicon-On-Insulator) erarbeitet. Erstmals wurden HBTs mit Grenzfrequenzen f T und f max
oberhalb von 200 GHz auf CMOS-kompatiblen SOISubstraten integriert.
1. Integration of extremely fast, complementary hetero-bipolar transistors.
We again succeeded in attaining a world-record value for the gate-delay times of silicon-based transistors. For npn-transistors with maximum transit and
oscillation frequencies of f T/f max = 300/250 GHz
and breakdown voltages of BVCE0 = 1.8 V gate-delays of 3.2 ps were attained. For pnp-transistors a
new world record of 5.9 ps was also attained with
f T/f max = 135/140 GHz and BVCE0 = 2.5 V.
In addition, a solution for the connection of highspeed HBTs and thin-layer-SOI-substrates (SiliconOn-Insulator) was developed. For the first time
HBTs with maximum frequencies of f T and f max over
200 GHz were integrated on CMOS-compatible
SOI-substrates.
2. Weiterentwicklung des kostengünstigen 0,25-µmSiGe:C-Prozesses (Value-Prozess).
Für den Prozess wurde im Jahr 2004 eine Leistungssteigerung durch zusätzliche Hetero-Bipolartransistoren mit Grenzfrequenzen von f T/f max =
130/150 GHz (zuvor 75/95 GHz) erreicht (eine Zusatzmaske erforderlich).
2. Further development of cost-effective 0.25 µm
SiGe:C processes (Value process).
An increase in performance was achieved for the
process in 2004 with additional hetero-bipolar
transistors with maximum frequencies of f T/f max =
130/150 GHz (previously 75/95 GHz) (an additional mask is required).
3. Demonstration einer Technologie mit integriertem
Flash Speicher.
Eine Technologie mit 1-Mbit-Flash-Speicher, integriert in eine 0,25-µm-BiCMOS, wurde entwickelt.
Das Integrationskonzept ist modular und erfordert
nur vier zusätzliche Maskenebenen. Besonderheit
der IHP-Lösung ist die einfache Integration von
Flash in eine leistungsfähige BiCMOS (Value Prozess) bei insgesamt geringen Kosten.
3. Demonstration of a technology with integrated
flash memory.
A technology with 1 Mbit flash memory, integrated
in a 0.25 µm BiCMOS, was developed. The integration principle is modular and requires only four
additional mask levels. A unique feature of the IHP
solution is the simple integration of flash in a powerful BiCMOS (Value process) with low overall
costs.
12
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Das Jahr 2004
Update 2004
4. Weltweite Nutzung der IHP-Technologien durch
MPW und Prototyping Service.
Die regelmäßigen Technologie-Shuttles am IHP ermöglichen Industriepartnern, Hochschulen und anderen Forschungseinrichtungen die Präparation innovativer Entwicklungsmuster und Prototypen. Derzeit arbeiten Designer aus mehr als 50 Einrichtungen mit dem Design-Kit des IHP. Seit Januar 2004
werden IHP-Technologien zusätzlich im Rahmen des
Europractice Services angeboten. Von den derzeitigen Nutzern ist mehr als die Hälfte aus der Industrie. Mehr als zwei Drittel der Nutzer stammen aus
Deutschland und Europa.
4. Worldwide use of IHP technologies by the MPW and
Prototyping Service.
The regular technology shuttles at IHP allow industrial partners, colleges and other research institutes to prepare innovative development samples
and prototypes. Designers are currently working
in more than 50 organizations with the IHP design
kit. As of January 2004 IHP technologies have also
been available in the framework of Europractice
Services. More than half of the current users are
from industry. More than two-thirds of the users
are from Germany and Europe.
5. BMBF-Projekt KOKON.
In diesem BMBF-Verbundprojekt testen deutsche
Automobilhersteller (DaimlerChrysler) und die Halbleiterindustrie (Bosch, Infineon und Atmel) gemeinsam
die Integration und Zuverlässigkeit von Si-Millimeterwellen-Schaltkreisen (MMIC) für die Anwendung
als Radar-Sende/Empfangseinheit (Anti-KollisionsRadar, Nahbereichs-Radar) im Frequenzbereich
76-81 GHz. Aufgaben des IHP in diesem Projekt
sind das Design von 78-GHz-VCO (spannungsgesteuerte Oszillatoren) und die Realisierung von
Hochfrequenzmessungen.
5. BMBF KOKON Project.
In this BMBF-cooperation project German automobile
producer (DaimlerChrysler) and the semiconductor
industry (Bosch, Infineon and Atmel) are jointly testing the integration and reliability of Si-millimeterwave integrated circuits (MMIC) for the application
as radar transmitter/receiver units (anti-collision
radar, close-range radar) in the frequency range
76-81 GHz. IHP’s task in this project is the design
of 78 GHz VCO (voltage-controlled oscillators) and
the realization of high-frequency measurements.
Materialien für die Mikroelektronik-Technologie
Materials for Microelectronics Technology
Die technologieorientierte Materialforschung des IHP
wurde im Jahr 2004 weiter ausgebaut. Es erfolgten inhaltliche Strukturierungen, Erweiterungen und Neuaufnahmen von Projekten. Beispiele dafür sind die Projekte zur siliziumbasierten Lichtemission sowie Projekte
zur Verbindung der Mikroelektronik mit der Biologie
und der Medizin.
In 2004, the technology oriented materials research
at IHP was intensifi ed. New projects commenced and
the contents of others restructured and expanded. Examples of these include projects for silicon-based light
emission and projects for linking microelectronics with
biology and medicine.
Beispiele für Ergebnisse im Jahr 2004 sind:
Examples of results in 2004 were:
1. Grundlagenuntersuchungen zu neuen Isolator-Materialien hoher Dielektrizitätskonstante auf Basis von
Praseodym.
Neben Praseodymoxid wurden im Rahmen eines
DFG-Projektes Schichten aus Praseodym-Silikat
als Isolator bzw. als Pufferschicht für Praseodymoxid entwickelt. Durch Hinzulegieren von Titan konnten die elektrischen Eigenschaften der Schichten
1. Basic research for new insulators of higher permittivity on the basis of praseodymium.
Along with praseodymium oxide, layers of praseodymium silicate were developed as an insulator
and as a buffer layer for praseodymium oxide in a
DFG-project. By alloying titanium the electrical properties of the layers could be improved and a higher
stability against atmospheric influences could be
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
13
Das Jahr 2004
Update 2004
verbessert und eine höhere Stabilität gegenüber
atmosphärischen Einflüssen erreicht werden. Es
wurden Schichten hergestellt, die bei einer äquivalenten Oxiddicke von 1,2 nm einen Leckstrom von
nur 10 -2 A/cm2 zeigen, der um zwei Größenordnungen kleiner ist als der für 2008 von der ITRS prognostizierte.
attained. Layers were produced which displayed a
leakage current of only 10 -2 A/cm2 with an equivalent oxide thickness of 1.2 nm; this is two magnitudes smaller than predicted by the ITRS for 2008.
2. Beginn einer Machbarkeitsstudie zum experimentellen Nachweis, ob und unter welchen Bedingungen es möglich ist, großflächige und defektfreie
alternative Silicon-On-Insulator (SOI) -Strukturen
mittels Molekularstrahlepitaxie (MBE) zu erzeugen.
Im Mittelpunkt der Untersuchungen steht das System Praseodymoxid/Silizium.
2. Beginning of a feasibility study to prove experimentally whether, and under what conditions, it is possible to create large area and defect-free alternative Silicon-On-Insulator (SOI) structures by means
of molecular beam epitaxy (MBE). The focus of the
experiment is on the praseodymium oxide/silicon
system.
3. Bewertung der Eignung einer siliziumbasierten
Lichtemission auf der Basis von ionenimplantierten LEDs für die optische Datenübertragung auf
Schaltkreisen.
Erreicht wurden Werte für die interne Quanteneffizienz bei Raumtemperatur von ca. 1% bei Bor-Implantation und 2% bei Phosphor-Implantation.
Durch Einbeziehung von SiGe-Schichten soll die
Wellenlänge der Lichtemission auf 1,5 µm verschoben werden. Wesentlicher Vorteil des am IHP untersuchten Verfahrens ist es, dass es kompatibel
zu existierenden Silizium-Technologien ist und das
der Betrieb der Lichtemitter mit Spannungen von
1-2 V möglich ist.
3. Evaluation of the suitability of a silicon-based light
emission on the basis of ion-implanted LEDs for the
optical data transmission in integrated circuits.
Values for the internal quantum efficiency at room
temperature of approx. 1% with boron implantation
and 2% with phosphorus implantation were obtained. By including SiGe layers, the wavelength of
the light emission should be shifted to 1.5 µm. The
most important advantage of the process investigated by IHP is that it is compatible with existing
silicon technologies and the operation of the light
emitter is possible with 1-2 volts.
4. Beginn mit Forschungsarbeiten, welche die Verbindung elektronischer und biologischer Technologien
zum Ziel haben.
Es wurde mit der Arbeit an einem durch die VWStiftung finanzierten Verbundprojekt begonnen,
das die definierte selbstorganisierte Anlagerung
von Biomolekülen an Silizium-Grenzflächen untersucht. Ausserdem wurde eine Studie zum Thema
„Zusammenarbeit der Materialforschung mit Biologie und Medizin“ erarbeitet.
4. Commencement of research which aims at linking
electronic and biological technologies.
The work on a VW Foundation sponsored cooperation project began. The project will investigate the
defined, self-organized deposit of biomolecules on
silicon interfaces. In addition, a study on the subject
“Cooperation of materials research with biology and
medicine” was developed.
14
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Das Jahr 2004
Update 2004
Brandenburgs Ministerpräsident Matthias Platzeck (Mitte) bei seinem Besuch am 6. August 2004 mit Frankfurts Oberbürgermeister Martin
Patzelt (links) und dem IHP-Geschäftsführer Prof. Dr. Wolfgang Mehr (rechts).
Brandenburg’s Prime Minister Matthias Platzeck (centre) at a visit on August 6, 2004 along with Frankfurt’s Mayor Martin Patzelt (left)
and the Director of IHP, Prof. Wolfgang Mehr (right).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
15
Angebote und Leistungen
Deliverables and Services
Angebote und
Leistungen
Deliverables and
Ser vices
Multiprojekt Wafer (MPW)
und Prototyping Service
Multiproject Wafer (MPW)
and Prototyping Service
Das IHP bietet seinen Kunden und Partnern Zugriff auf
seine leistungsfähige 0,25-µm-SiGe:C-BiCMOS-Technologien.
IHP offers customers and partners access to its powerful 0.25 µm SiGe:C BiCMOS technologies.
Die Technologien sind insbesondere für Anwendungen
im oberen GHz-Bereich geeignet, so z.B. für die drahtlose- und Breitbandkommunikation oder Radar. Sie
bieten integrierte HBTs mit Grenzfrequenzen bis zu
220 GHz und integrierte HF LDMOS Bauelemente mit
Durchbruchspannungen bis zu 26 V einschließlich komplementärer Bauelemente.
The technologies are suited to applications in the higher GHz bands (e.g. for wireless, broadband, radar).
They offer integrated HBTs with cut-off frequencies
of up to 220 GHz and RF LDMOS devices with breakdown voltages up to 26 V, including complementary
devices.
Verfügbar sind folgende vier Technologien:
The following four technologies are available:
SG25H1:
Eine Hochleistungs-Technologie mit npnHBTs bis zu f T/f max = 180/220 GHz.
SG25H1:
A high-performance technology with npnHBTs up to f T/f max = 180/220 GHz.
SG25H2:
Eine komplementäre Hochleistungs-Technologie mit npn-HBTs ähnlich SG25H1
und zusätzlichen pnp-HBTs mit f T/f max =
90/125 GHz.
SG25H2:
A complementary high-performance technology with npn-HBTs comparable to
SG25H1 and additional pnp-HBTs with
f T/f max = 90/125 GHz.
SG25H3:
Eine Technologie mit mehreren npn-HBTs,
deren Parameter von einer höheren HF
Performance (f T/f max = 110/190 GHz) zu
höheren Durchbruchspannungen bis zu 7 V
reichen.
SG25H3:
A technology with a set of npn-HBTs,
ranging from a higher RF performance
(f T/f max = 110/190 GHz) to higher breakdown voltages up to 7 V.
SGB25VD: Eine kostengünstige Technologie mit mehreren npn-Transistoren mit Durchbruchspannungen bis zu 7 V. Eine Besonderheit
dieser Technologie sind zusätzliche integrierte komplementäre HF LDMOS Bauelemente mit Durchbruchspannungen bis zu
26 V.
SGB25VD: A cost-effective technology with a set of
npn-HBTs up to a breakdown voltage of 7 V.
A distinctive feature of this technology is
additional integrated complementary RF
LDMOS devices with breakdown voltages
up to 26 V.
Die Technologiefamilie SGC25 des IHP (SGC25A,
SGC25B, SGC25C) wird weiterhin genutzt, aber derzeit durch die neue Familie SG25H mit verbesserten
Parametern und zusätzlichen Leistungen ersetzt.
IHP’s SGC25-family of technologies (SGC25A, SGC25B,
SGC25C) is still running but is currently being replaced
by the new SG25H-family with improved parameters
and additional features.
Ausserdem entwickelt das IHP eine 0,13-µm-BiCMOSTechnologie als nächste Generation.
In addition, the IHP is developing a 0.13 µm BiCMOS
technology as next generation.
Es finden technologische Durchläufe nach einem festen, unter www.ihp-microelectronics.com verfügbaren
Zeitplan statt.
Runs start on a regular basis. The schedule is available at www.ihp-microelectronics.com.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
17
Angebote und
Leistungen
Deliverables and
Ser vices
Ein Cadence-basiertes Design-Kit für Mischsignale ist
verfügbar. Wiederverwendbare Schaltungsblöcke und
IPs des IHP für die drahtlose und Breitbandkommunikation können zur Unterstützung von Kundendesigns
verwendet werden.
A cadence-based mixed signal design kit is available.
IHP’s reusable blocks and IPs for wireless and broadband can support customer designs.
In den folgenden Tabellen sind die wesentlichen Parameter der für MPW und Prototyping angebotenen Technologien dargestellt:
Technical key-parameters of the technologies offered
for MPW and Prototyping are:
1. 0,25-µm-Hochleistungs-SiGe:C-BiCMOS-Technologie (SG25H1).
1. High-Performance 0.25 µm SiGe:C BiCMOSTechnology (SG25H1).
Parameter
Value
AE
0.18 x 0.84 µm2
Peak f max
220 GHz
Peak f T
180 GHz
BVCE0
1.9 V
VA
40
č
200
Bipolar Section
CMOS Section (0.25 µm)
Core Supply Voltage
2.5 V
nMOS V th
0.6 V
I Dsat
540 µA/µm
I off
3 pA/µm
-0.56 V
pMOS V th
I Dsat
230 µA/µm
I off
3 pA/µm
Passives
1 fF/µm2
MIM Capacitor
18
N + Poly Resistor
210 Ý/[]
P+ Poly Resistor
280 Ý/[]
High Poly Resistor
1600 Ý/[]
Varactor Cmax /Cmin
3
Inductor [email protected] GHz
12 (1 nH), 6 (15 nH)
Inductor [email protected] GHz
16 (1 nH), 10 (2 nH)
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Angebote und
Leistungen
2. Komplementäre 0,25-µm-Hochleistungs-SiGe:CBiCMOS-Technologie (SG25H2).
Parameter
Bipolar Section
Deliverables and
Ser vices
2. Complementary High-Performance 0.25 µm
SiGe:C BiCMOS (SG25H2).
npn
pnp
0.21 x 0.84 µm2
AE
Peak f max
180 GHz
125 GHz
Peak f T
180 GHz
90 GHz
BVCE0
1.9 V
2.5 V
VA
40
30
č
160
100
Diese Bauelemente ersetzen den Bipolarteil von
SG25H1. Der CMOS-Teil und die passiven Bauelemente sind identisch mit SG25H1.
Replaces bipolar section of SG25H1; CMOS section
and passives are identical to SG25H1.
3. 0,25-µm-SiGe:C-BiCMOS-Technologie mit mehreren npn-HBTs im Bereich von hoher HF Performance bis zu höheren Durchbruchspannungen
(SG25H3).
3. 0.25 µm SiGe:C BiCMOS with a set of npn-HBTs,
ranging from high RF performance to higher
breakdown voltages (SG25H3).
Parameter
High
Performance
High
Performance SHP
Medium
Voltage
High
Voltage
AE
0.21 x 0.84 µm2
0.42 x 0.84 µm2
0.21 x 0.84 µm2
0.21 x 0.84 µm2
Peak f max
190 GHz
140 GHz
140 GHz
80 GHz
Peak f T
110 GHz
120 GHz
45 GHz
25 GHz
BVCE0
2.0 V
2.3 V
5V
7V
Bipolar Section
VA
30
30
30
30
č
150
150
150
150
Die Bauelemente ersetzen den Bipolarteil von SG25H1.
Der CMOS-Teil und die passiven Bauelemente sind identisch mit SG25H1.
Replaces bipolar section of SG25H1; CMOS section
and passives are identical to SG25H1.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
19
Angebote und
Leistungen
Deliverables and
Ser vices
4. 0,25-µm-SiGe:C-BiCMOS-Technologie mit Bauelementen für höhere Spannungen (SGB25VD).
4. 0.25 µm SiGe:C BiCMOS with High-Voltage Devices (SGB25VD).
Die Technologie enthält neben HBTs auch komplementäre HF LDMOS Bauelemente. In den folgenden zwei
Tabellen sind wichtige Parameter zusammengefaßt.
In addition to HBTs the technology also has complementary RF LDMOS. Key parameters are summarized
in the following two tables.
High
Performance
Parameter
Standard
High
Voltage
Bipolar Section
0.5 x 0.9 µm2
AE
Peak f max
95 GHz
90 GHz
70 GHz
Peak f T
75 GHz
45 GHz
25 GHz
BVCEO
2.4 V
4.0 V
7.0 V
BVCBO
>7V
> 15 V
> 20 V
VA
>50 V
>80 V
>100 V
190
č
CMOS Section (0.25 µm)
Core Supply Voltage
nMOS V th
2.5 V
0.61 V
I Dsat
570 µA/µm
I off
3 pA/µm
-0.51 V
pMOS V th
I Dsat
290 µA/µm
I off
3 pA/µm
Passives
1 fF/µm2
MIM Capacitor
+
P Poly Resistor
310 Ý/[]
High Poly Resistor
2000 Ý/[]
Varactor Cmax /Cmin
3
Inductor [email protected] GHz
12 (1 nH), 6 (15 nH)
Inductor [email protected] GHz
16 (1 nH), 10 (2 nH)
n-LDMOS 23
n-LDMOS
I10****
p-LDMOS
p-LDMOS 8
p-LDMOS 12
BV DSS*
26 V
16 V
11.5 V
-11 V
-13.5 V
I Dsat**
140 µA/µm
(VGS = 1.5 V)
140 µA/µm
(VGS = 1.5 V)
175 µA/µm
(VGS = 1.5 V)
85 µA/µm
(VGS = -1.5 V)
90 µA/µm
(VGS = -1.5 V)
I leakage
< 15 pA/µm
(V DS = 20 V)
< 15 pA/µm
(V DS = 10 V)
< 15 pA/µm
(V DS = 8 V)
< 50 pA/µm
(V DS = -8 V)
< 50 pA/µm
(V DS = -8 V)
R ON
11 Ýmm
7 Ýmm
7.5 Ýmm
16 Ýmm
11.5 Ýmm
Peak f max***
40 GHz
43 GHz
46 GHz
21 GHz
22 GHz
19 GHz
23 GHz
21 GHz
8 GHz
11 GHz
Peak f T***
*:@100 pA/µm
20
n-LDMOS
n-LDMOS 13
**:@V DS = 5 V ***:@V DS = 4 V ****: substrate isolated
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Angebote und
Leistungen
Deliverables and
Ser vices
Design Kit
Design Kit
Die Design Kits unterstützen eine Cadence MischsignalPlattform:
The design kits support a Cadence mixed signal platform:
-
Design Framework II (Cadence 4.4.6)
-
Design Framework II (Cadence 4.4.6)
-
Verhaltens-Beschreibung (Verilog HDL)
-
Behavioral Modeling (Verilog HDL)
-
Logische Synthese und Optimierung (VHDL/HDL
Compiler, Design Compiler/Synopsys, Power Compiler/Synopsys)
-
Logic Synthesis and Optimization (VHDL/HDL Compiler, Design Compiler/Synopsys, Power Compiler/
Synopsys)
-
Test Generation/Synthetisierer/Test Compiler (Synopsys)
-
Test Generation/Synthesizer/Test Compiler (Synopsys)
-
Simulation (RF: SpectreRF, Analog: SpectreS, Verhaltens-Beschreibung/Digital: Leapfrog/NC-Affirma/ Verilog-XL/ModelSim)
-
Simulation (RF: SpectreRF, Analog: SpectreS, Behavioral/Digital: Leapfrog/NC-Affi rma/Verilog-XL/
ModelSim)
-
Platzieren und verbinden (Silicon Ensemble und
Preview)
-
Place and Route (Silicon Ensemble and Preview)
-
Layout (Virtuoso Editor-Cadence)
-
Layout (Virtuoso Editor - Cadence)
-
Verifizierung (Diva and Assura: DRC/LVS/Extract/
Parasitic Extraction)
-
Verification (Diva and Assura: DRC/LVS/Extract/
Parasitic Extraction)
-
ADS-Support über RFDE/RFIC mit dynamischem
Link zu Cadence ist verfügbar
-
ADS-support via RFDE/RFIC dynamic link in Cadence is available
-
Ein eigenständiges ADS Kit einschließlich Momentum Substrate Layer File wird unterstützt, jedoch
ohne Layout-Unterstützung.
-
A standalone ADS Kit including Momentum substrate layer file is supported but without layout
support.
Transfer von Technologien und
Technologie-Modulen
Transfer of Technologies and
Technology Modules
Das IHP bietet den Transfer seiner 0,25-µm-BiCMOSTechnologien und Technologiemodule (HBT, LDMOS) an.
Die technologischen Parameter entsprechen weitgehend den oben für MPW und Prototyping genannten.
Für die Technologie SGB25VD sind ausserdem Bauelemente mit höherer als der genannten Performance
verfügbar.
IHP offers its 0.25 µm BiCMOS technologies and technology modules (HBT-Modules, LDMOS-Modules) for
transfer.
The technological parameters comply to a large extent
with the parameters described above for MPW and
Prototyping. In the case of SGB25VD, devices with a
higher performance are available.
Verfügbare Blöcke und Designs für
die drahtlose und Breitbandkommunikation
Available Blocks and Designs for
Wireless and Broadband
Zur Unterstützung von Kundendesigns bietet das IHP
Schaltungsblöcke und Schaltungen für Lösungen im
Bereich drahtlose und Breitbandkommunikation an:
To support customer designs, IHP offers a wide range of blocks and designs for wireless and broadband
solutions:
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
21
Angebote und
Leistungen
Deliverables and
Ser vices
-
Bluetooth Transceiver und Komponenten wie LNAs,
Mischer, VCOs, Teiler, Prescaler, Demodulatoren,
Frequenzsynthesizer und Zwischenfrequenz-Verstärker
-
Bluetooth transceivers and components, such as
LNAs, mixer, VCOs, dividers, prescalers, demodulators, frequency synthesizers, and IF amplifiers
-
2,4-GHz-Single-Chip PA/LNA/RX/ TX-Switch in hybrider Technologie
-
Hybrid 2.4 GHz single-chip PA/LNA/RX/TX-switch
-
5-GHz- (IEEE 802.11a, HiperLAN/2) -Single-ChipTransceiver und Komponenten wie z.B. 5 GHz
VCOs, Polyphasenfilter, Zwischenfrequenz AbwärtsMischer, spannungsgesteuerte Verstärker, aktive
Basisband-Filter, Synthesizer, I2C-Bus Interface;
vollständiger Single-Chip IP-Block
-
5 GHz (IEEE 802.11a, HiperLAN/2) single-chip
transceiver and components, such as 5 GHz VCOs,
polyphase fi lters, IF down mixers, gain controlled
amplifi ers, active baseband fi lters, synthesizer, and
I2C-Bus interface; full single-chip IP block
-
UWB Pulsgenerator; UWB LNA
-
UWB puls generator; UWB LNA
-
24-GHz-Mischer, 24-GHz-VCO
-
24 GHz mixer, 24 GHz VCO
-
Statische und dynamische Teilerschaltungen bis zu
60-GHz; 60-GHz-LNA, PLL, Mischer und VCO
-
Static and dynamic divider circuits for up to 60 GHz;
60 GHz LNA, PLL, mixer, VCO
-
76-GHz-LC-Oscillator
-
76 GHz LC-oscillator
-
SPW (Signal Processing Worksystem) und MATLAB-Modelle für einen digitalen Basisband-Prozessor für ein IEEE 802.11a-konformes Modem einschliesslich der Einheiten für Synchronisation und
Kanalschätzung
-
SPW (Signal Processing Worksystem) and MATLAB
models of a digital baseband processor for an IEEE
802.11a compliant modem, including the synchronization and channel estimation units
-
Designs für Basisband-Verarbeitung (Viterbi Decoder, FFT/IFFT Prozessor, CORDIC Prozessor)
-
Designs for baseband processing (Viterbi decoder,
FFT/IFFT processor, CORDIC processor)
-
Synthetisierbares VHDL Modell des kompletten
IEEE 802.11a OFDM Basisband-Prozessors einschliesslich der Synchronisation und Kanalschätzung
-
Synthesizable VHDL model of the complete IEEE
802.11a OFDM baseband processor including synchronization and channel estimation
-
Ein abstraktes SDL-Modell des MAC-Layer für ein
IEEE 802.11a-kompatibles Modem mit Testbenches für verschiedene Anwendungs-Szenarien
-
Abstract SDL model of MAC layer for IEEE 802.11a
compliant modem with testbenches for various deployment scenarios
-
Echtzeit-Implementierung des MAC-Layer für ein
IEEE 802.11a-kompatibles Modem für eingebettete Anwendungen, bestehend aus einem auf MIPSoder ARM-Prozessoren laufenden C-Programm, sowie einem speziellen Hardware-Beschleuniger
-
Realtime implementation of the MAC layer for an
IEEE 802.11a compliant modem for embedded
applications consisting of a C-program running on
MIPS or ARM processors, and a dedicated hardware accelerator
-
Ein abstraktes SDL-Modell der MAC-Layer für ein
HiperLAN/2-kompatibles Modem mit Testbenches
für verschiedene Szenarien der Implementierung
-
Abstract SDL model of MAC layer for HiperLAN/2
compliant modem with testbenches for various deployment scenarios
-
Ein abstraktes SDL-Modell für IEEE 802.15.3 und
IEEE 802.15.4
-
Abstract SDL model for IEEE 802.15.3 and IEEE
802.15.4
-
5-GHz-Link-Emulator und Entwicklungsumgebung
für WLAN
-
5 GHz link emulator and WLAN design/debug kit
-
TCP/IP-Prozessor einschließlich Hardware-Beschleuniger.
-
TCP/IP-processor including hardware accelerator.
22
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Angebote und
Leistungen
Deliverables and
Ser vices
Unterstützung bei Prozess-Modulen
Process Module Support
Das IHP bietet Unterstützung bei der Realisierung spezieller Prozess-Module für Forschung und Entwicklung
und für Prototyping bei geringen Volumina für Standard-Prozess-Module und Prozess-Schritte.
IHP offers support for advanced process modules for
research and development purposes and small volume
prototyping for standard process modules and process steps.
Verfügbar sind u.a. folgende Prozess-Module:
Process modules available include:
-
Standard-Prozesse (Implantation, Ätzen, CMP und Abscheidung von Standard-Schichten und Schichtstapeln wie thermisches SiO2, PSG, Si3N4, Al, TiN, W)
-
Standard processes (implantation, etching, CMP
and deposition of standard layers and layer stacks
such as thermal SiO2, PSG, Si 3 N 4, Al, TiN, W)
-
Standard- und Niedertemperatur-Epitaxie (Si, Si:C,
SiGe, SiGe:C)
-
Standard and low-temperature epitaxy (Si, Si:C,
SiGe, SiGe:C)
-
Optische Lithographie (i-Linie und 248 nm bis hinab
zu 100 nm Strukturgröße)
-
Optical lithography (i-line and 248 nm down to 100 nm
structure size)
-
Verkürzte Prozessabläufe.
-
Short-flow processing.
Fehleranalyse und Diagnostik
Failure Mode Analysis and Diagnostics
Das IHP bietet Unterstützung bei der Ausbeuteerhöhung durch Fehleranalyse mit modernen Ausrüstungen wie z.B. AES, AFM, FIB, LST, REM, SIMS, STM
und TEM.
IHP offers support for yield enhancement through failure mode analysis with state-of-the-art equipment,
including AES, AFM, FIB, LST, SEM, SIMS, STM and
TEM.
Für weitere Informationen wenden Sie sich bitte an:
For more information please contact:
Dr. Wolfgang Kissinger
IHP GmbH
Im Technologiepark 25
15236 Frankfurt (Oder), Germany
Email
[email protected]
Telefon +49 335 56 25 410
Telefax +49 335 56 25 222
Dr. Wolfgang Kissinger
IHP GmbH
Im Technologiepark 25
15236 Frankfurt (Oder), Germany
Email
[email protected]
Phone +49 335 56 25 410
Fax
+49 335 56 25 222
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
23
Forschung des IHP
IHP’s Research
Forschung des IHP
IHP‘s Research
Das IHP arbeitet an drei eng miteinander verbundenen Forschungsprogrammen. Gemeinsames Ziel ist
die Schaffung innovativer Lösungen für Anwendungen
in den Bereichen drahtlose und Breitbandkommunikation.
IHP is working on three closely connected research
programs. The joint objective is the creation of innovative solutions for wireless and broadband applications.
So verfügt das Institut über eine Pilotlinie für seine
eigenen Forschungs- und Entwicklungsprojekte sowie
für die Präparation von Chips für Projekte und Entwicklungen Dritter. Eine weitere Besonderheit ist das vertikale Forschungskonzept des IHP unter Nutzung der
zusammenhängenden und aufeinander abgestimmten
Kompetenzen des Institutes auf den Gebieten System
Design, Design von Hochfrequenzschaltungen, Halbleitertechnologie und Materialforschung.
The institute has a pilot line for its own research and
development projects as well as for preparing chips
for projects and developments of third parties. An additional speciality is IHP’s vertical research concept
employing the associated and harmonized competences of the institute in the fields of system design,
design of RF circuits, semiconductor technology and
materials research.
Die Forschung des IHP setzt ebenso auf die typischen
Stärken eines Leibniz-Institutes: Sie ist charakterisiert
durch eine langfristige, komplexe Arbeit, die Grundlagenforschung mit anwendungsorientierter Forschung
verbindet.
The research of the IHP is based on the typical
strengths of a Leibniz Institute; it is dominated by
long-term, complex efforts which connect basic research with application-oriented research.
Die Realisierung der Forschungsprogramme erfolgt
mit Hilfe eines regelmäßig aktualisierten Portfolios
von Projekten. Die Aktualisierung erfolgt aufgrund inhaltlicher Erfordernisse sowie der Möglichkeiten für
Kooperationen und Finanzierung. Projekte mit der Industrie und Drittmittelprojekte werden im Einklang mit
den strategischen Zielen des IHP eingeworben.
The realization of the programs is accomplished
through a project portfolio which is regularly updated
according to the content requirements as well as
through opportunities for cooperations and outside
funding. Industry and grant projects are acquired in
such a manner as to serve the strategic goals of IHP.
Im Folgenden werden wesentliche Zielstellungen der
Forschungsprogramme des IHP beschrieben.
Significant goals of IHP’s research programs are specified below.
Drahtloses Internet: Systeme und
Anwendungen
Wireless Internet: Systems and
Applications
In diesem Programm werden komplexe Systeme für
das drahtlose Internet in Form von Prototypen und Anwendungen untersucht und entwickelt. Ziel sind Hardware/Software-Systemlösungen auf hochintegrierten
Single-Chips. Unser vertikaler Forschungsansatz zeigt
sich auch in der Architektur der erarbeiteten Systeme.
Im Wesentlichen optimieren wir die Wechselwirkung
zwischen den Schichten und realisieren eine vertikale
Migration der semantischen Elemente.
Die drei Hauptforschungsrichtungen sind Systeme mit
hoher Performance, Systeme mit geringem Energieverbrauch und Middleware für kontextabhängige Anwendungen.
This program investigates and develops complex systems for wireless Internet as prototypes and applications with the objective to find solutions for Hardware/
Software systems on highly integrated single chips.
Our vertical approach is also reflected in the architecture of the addressed systems. Basically, we optimize
interlayer interaction and perform vertical migrations
of semantic elements.
The three major directions of research are systems
with high performance, systems with low power consumption and middleware systems for context sensitive applications.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
25
Forschung des IHP
IHP‘s Research
Für drahtlose Systeme mit hoher Performance ist es
das Ziel, alle Funktionen eines drahtlosen PDA auf ein
Chip zu integrieren. Dabei sollen Datenraten bis 1 Gbps
bei Trägerfrequenzen bis zu 60 GHz erreicht werden.
The goal for high-performance wireless systems is to
integrate all functionalities of a wireless PDA on a single chip. The targets are to achieve a data rate of up
to 1 Gbps at carrier frequencies of up to 60 GHz.
Die Forschung zu Systemen mit geringem Energieverbrauch hat zum Ziel, Sensornetze auf einem Chip zu
realisieren. Typische Anwendungen dafür sind BodyArea Netze für medizinische Anwendungen oder Wellness.
The research on systems with low energy consumption is directed towards sensor networks on single
chips. Typical applications are body-area networks for
health care or wellness.
Die Forschung zu kontextabhängigen MiddlewareSystemen betrifft insbesondere auch die Erhaltung
der Privatsphäre und die Sicherheit bei der Nutzung
mobiler Endgeräte. Darüber hinaus wird die symmetrische bzw. asymmetrische Verteilung von Ressourcen
zwischen Endgeräten und Servern im Gesamtsystem
untersucht.
Research in context-sensitive middleware systems
addresses privacy and security questions in using mobile devices. Moreover we investigate symmetrical and
asymmetrical resource distribution between client and
server parts of the overall system.
Technologieplattform für drahtlose
und Breitbandkommunikation
Technology Platform for Wireless
and Broadband
In diesem Programm sollen Technologien mit zusätzlichen Funktionen entwickelt werden, insbesondere
durch die Erweiterung industrieller CMOS-Technologien
mit integrierten Modulen. Die Hauptforschungsrichtungen in diesem Programm sind Technologien mit hoher
Performance, kostengünstige Technologien und System-on-Chip, sowie die Sicherung des Zugriffs interner
und externer Designer auf die Technologien des IHP.
The aim of this program is to develop value-added
technologies, preferably BiCMOS technologies, by
modular extension of industrial CMOS processes with
integrated modules. The major directions of the research in this program are technologies with a high
performance, low-cost technologies including systemon-chip, and the provision of technology access for internal and external designers.
Die Forschung in Richtung Technologien hoher Performance zielt auf extrem schnelle SiGe:C-HBTs, einschließlich komplementärer Bauelemente und neuer
Bauelementekonzepte für Anwendungen bei Frequenzen bis oberhalb 100 GHz.
The research towards high-performance technologies
targets ultrafast SiGe:C HBTs, including complementary devices and new device concepts, for applications at frequencies of 100 GHz and more.
Zielstellung der Forschung für kostengünstige Technologien ist es, kostengünstige BiCMOS-Technologien zu entwickeln und darin zusätzliche Module wie
HF LDMOS, Flash und passive Bauelemente zu integrieren.
The aim of the research for low-cost technologies is
to develop low-cost BiCMOS and to integrate additional modules such as RF LDMOS, Flash and passive
devices.
Gegenwärtig wird der Zugriff auf die 0,25-µmBiCMOS-Technologien gesichert. Für die entsprechenden technologischen Durchläufe in der Pilotlinie in
Frankfurt (Oder) existiert ein fester Zeitplan.
Eine neue 0,13-µm-BiCMOS-Technologie ist in Entwicklung.
Access is provided to the 0.25 µm BiCMOS technologies currently available. Runs in IHP’s pilot line in
Frankfurt (Oder) start on a regular basis.
A new 0.13 µm SiGe:C BiCMOS technology is under
development.
26
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Forschung des IHP
IHP‘s Research
Materialien für die MikroelektronikTechnologie
Materials for Microelectronics Technology
Die Materialforschung am IHP hat die Integration neuer
Materialien in die Technologie zum Ziel, um so zusätzliche oder bessere Funktionalitäten zu erreichen.
Außerdem bereitet die Materialforschung neue Forschungsgebiete am IHP vor.
Materials research at IHP targets the integration of
new materials into the technology to achieve additional
or better functionalities. It is also geared towards the
preparation of new research fields at the institute.
Derzeit ist die Auswahl und Fertigung von Isolatoren
hoher Dielektrizitätskonstante ein Schwerpunkt der
Materialforschung am IHP. Anwendungsspezifische
Entwicklungen dieser Isolatoren für MIMs (Metall Isolator Metall), Speicher und CMOS werden gemeinsam
mit den Technologen des IHP bzw. mit industriellen
Partnern realisiert.
Currently, the selection and manufacturing of insulators with high permittivity is one focal point of IHP’s
materials research. Application-specific developments
of these insulators for MIMs (metal insulator metal),
memory and CMOS are realized together with IHP’s
technology department or with industrial partners.
Eine Anzahl kleinerer Projekte wird auf neuen und aussichtsreich erscheinenden Gebieten durchgeführt. Bei
erfolgversprechenden Ergebnissen werden sie mit
höherer Kapazität fortgesetzt. Beispiele für derartige Forschungsgebiete sind die Integration optischer
Datenübertragung in der Mikroelektronik oder die Zusammenführung der Mikroelektronik mit der Biologie
oder medizinischen Anwendungen.
A spectrum of smaller projects is conducted in new
and promising areas. In successful cases they are
then worked on with increased capacity. Examples of
promising research areas include the integration of
optical data transmissions in microelectronics and the
combination of microelectronics with biology or medical applications.
Auf den folgenden Seiten sind ausgewählte Projekte
der Forschungsprogramme des IHP beschrieben.
On the following pages you will find a description of selected projects from IHP’s research programs.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
27
Ausgewählte Projekte
Selected Projects
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
Drahtloses Internet/
Wireless Internet
Mobile Business Engine
Mobile Business Engine
Im Rahmen des Projektes Mobile Business Engine wird
eine Middleware-Plattform entwickelt, die die Realisierung kontext-sensitiver Dienste unterstützt, die sicher
sind und die Privatsphäre garantieren.
The Project Mobile Business Engine is developing a
middleware platform for context aware services which
provides the means to ensure secure communication
as well as privacy of service users.
Das Zusammenwachsen von Mobilkommunikation und
Internet bietet die Möglichkeit, neuartige Dienste, Arbeitsabläufe und Geschäftsmodelle zu realisieren. Eine
möglichst weitreichende Nutzung der sich hieraus ergebenden Möglichkeiten kann nur dann erreicht werden, wenn die Entwicklung neuartiger Dienste auf einem ausreichend hohen Abstraktionsniveau erfolgt
und wenn geschäftliche sowie private Daten gegen
Abhören, Verfälschen, Missbrauch etc. geschützt werden. Durch den Einsatz geeigneter kryptographischer
Massnahmen ist dies möglich, doch steigt dadurch der
Energieverbrauch. Der Nutzer mobiler Endgeräte ist
somit i.d.R. gezwungen, sich zwischen einer sicheren
Kommunikation und der möglichst langen Verfügbarkeit seines Endgerätes zu entscheiden. Dieser Konflikt
kann durch den Einsatz energieeffizienter Hardwarebeschleuniger für kryptographische Verfahren gelöst
werden.
The convergence of mobile communication and Internet
allows new kind of services and business models to be
realized and company employees, who are working remote, to be integrated. These opportunities can be exploited fully only if new services and applications can
be developed at a suffi ciently high level of abstraction.
In addition, business and private data have to be protected against eavesdropping, tampering, profi ling etc.
Applying cryptographic means provides such security
mechanisms but it also increases the energy consumption of the mobile devices signifi cantly. Thus, the user
has to decide between a convenient uptime of the mobile device and a secure communication. This confl ict
can be solved applying energy effi cient hardware accelerators for cryptographic means.
Um eine sichere Kommunikation gewährleisten zu können, werden symmetrische und asymmetrische Verschlüsselungsverfahren benötigt. Die symmetrischen
Verfahren werden zur Verschlüsselung der Daten eingesetzt, während die asymmetrischen Verfahren zur
Authentisierung der Kommunikationspartner, zur Erzeugung digitaler Unterschriften und zum Austausch
von Schlüsseln für symmetrische Verfahren eingesetzt
werden. Im Bereich der symmetrischen Verfahren wird
der Advanced Encryption Standard (AES) genutzt. Es
gibt bisher keinen erfolgreichen Angriff, so dass AES
eine lange Nutzungsdauer erlaubt. Ziel der Arbeiten
war es, eine AES-Implementierung mit geringem Flächenbedarf zu erarbeiten, um so geringe Fertigungskosten zu gewährleisten. Die Parameter des AES-Hardwarebeschleunigers sind in Tabelle 1 dargestellt.
Die elliptische Kurven-Kryptographie (ECC) wurde als
asymmetrisches Verfahren gewählt, weil hier der Rechenaufwand deutlich geringer ist als beim Einsatz
In order to ensure secure communication, public as
well as secret key cryptography has to be applied. Secret key mechanisms are used for bulk data transfer,
whereas public key approaches are used for mutual
authentication, digital signatures as well as for secret key exchange. We use AES (Advanced Encryption
Standard) as a secret key mechanism. Up to now there has been no known successful attack on AES, so it
can be used for a reasonable period of time. Our main
goal was to develop an area-efficient AES implementation in order to guarantee low manufacturing costs.
Table 1 illustrates the characteristics of the AES hardware accelerator.
As a public key mechanism we selected Elliptic Curve
Cryptography (ECC). The computational burden that
is inhibited by ECC is less than that of RSA, the most
commonly used encryption and authentication algorithm. ECC provides the same level of security as RSA
but with a significantly shorter key length, so ECC is
well suited for application in mobile communication.
The main operation in ECC is the ‘kP’ multiplication.
The complexity of this multiplication can be reduced
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
29
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
AES (128bit)
42 Mbps
Throughput @ 33 MHz
ECC (233bit)
0.85 Mbps
Power consumption @ 33 MHz
9.59 mW
56.85 mW
Complexity
14.44 Kgates
27.26 Kgates
Rate
100 clock cycles
9000 clock cycles
Size (@ 0.25 µm technology)
1.01 mm2
2.11 mm2
Tabelle 1: Eckdaten der beiden Hardwarebeschleuniger.
Table 1: Characteristics of both hardware accelerators.
von RSA, dem verbreitetsten Verfahren für Verschlüsselung und Authentisierung. Außerdem bietet ECC
die gleiche Sicherheit wie RSA bei deutlich kürzerer
Schlüssellänge, d.h. ECC ist für den Einsatz im Mobilbereich besonders geeignet. Die wichtigste Basis-Operation ist die ‚kP’-Multiplikation. Die Komplexität dieser
Operation kann mit Hilfe der Karatsuba-Methode, die
i.d.R. rekursiv angewendet wird, reduziert werden. Im
Rahmen des Projektes Mobile Business Engine wurde
eine iterative Anwendung der Karatsuba-Methode entwickelt, die die Realisierung von Hardware-Beschleunigern mit geringem Flächenbedarf erlaubt. Das gleiche
Vorgehen wurde auch für andere rekursive Verfahren,
die auf dem Karatsuba-Verfahren beruhen, untersucht.
Die iterativen Varianten haben einen bis zu 60 Prozent
geringeren Flächenbedarf als die rekursiven Versionen.
Der Energiebedarf für die Multiplikationen ist bei einigen Varianten ebenfalls um 30 Prozent geringer als bei
der günstigsten rekursiven Variante. Tabelle 1 zeigt
die Parameter der tatsächlich gefertigten Variante.
Sowohl der AES- als auch der ECC-Hardwarebeschleuniger sind bereits am IHP gefertigt worden. Beide wurden in einen gemeinsamen Chip integriert, der darüber
hinaus über eine PCMCIA- und eine CardBus-Schnittstelle zur Einbindung in mobile Endgeräte verfügt.
Abb. 1 zeigt das Chipfoto. Die Parameter der beiden
Hardwarebeschleuniger belegen eindeutig, dass weder die Herstellungskosten noch der Energieverbrauch
einem Einsatz der Hardwarebeschleuniger in mobilen
Endgeräten entgegen stehen.
Abb. 1:
Fig. 1:
30
by applying the Karatsuba method. Normally the Karatsuba approach is applied recursively. In the Mobile
Business Engine project we developed an iterative implementation of the Karatsuba method, which allows
area efficient hardware accelerators for the ‘kP’ multiplication to be realized. We also investigated our idea
for other recursive approaches which are based on the
Karatsuba method. The hardware accelerators which
are realized when adopting an iterative approach take
up to 60 per cent less area and some versions use
about 30 per cent less energy per multiplication than
the recursive variants. The parameters of the manufactured version are shown in table 1.
Both hardware accelerators have already been integrated into one chip, which also provides a PCMCIA
and a CardBus interface for integration of the chip into
mobile devices. Fig. 1 shows a photo of this chip. The
characteristics of both hardware accelerators clearly indicate that neither the cost nor the energy consumption prohibits the use of hardware accelerators
in mobile devices.
Chipfoto des Dual Krypto Chips.
Chip photo of the dual crypto chip.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
TCP/IP-Kommunikations-Chip
TCP/IP Communication Chip
Ziel des Projektes ist es, das TCP/IP-Protokoll mittels
einer Hardwarelösung bei hohen Datenraten und reduziertem Stromverbrauch zu unterstützen.
The goal is to enable TCP/IP with dedicated hardware,
by means of a communication chip which can support
high data rates at minimal power consumption.
TCP/IP ist das zentrale Protokoll im Internet. Im Zuge
der Entwicklung werden zunehmend kleinere und unterschiedlichere Geräte an das Internet angeschlossen,
welche nur über geringe Energiequellen verfügen. So
stellt z.B. für PDAs und Laptopcomputer das TCP/IPProtokoll eine erhebliche Belastung der Systemressourcen dar. Mittels speziell entwickelter Hardware
wird diese Last reduziert und effizienter Datentransfer bei hohen Datenraten ermöglicht. Außerdem kann
man auf diese Art „dumme“ Geräte ohne eigene CPU
an das Internet anschließen.
TCP/IP is the central protocol used on the Internet.
The trend is to connect smaller and more diverse devices with limited processing power and battery supplies. TCP/IP processing is a substantial load on the
system resources, especially for mobile devices such
as PDAs or laptops. A hardware TCP/IP processor reduces the burden while supporting data transfer at
high throughput. In addition, such a hardware solution
can enable a more primitive device to be developed
with none or only a small CPU with Internet access in
the sense of “ubiquitous computing”.
Das Projekt hat hierzu einen Chip mit einer Systemarchitektur wie in Abb. 2 dargestellt entwickelt. Der Chip
benötigt Schnittstellen sowohl nach oben als auch
nach unten, da die mittleren Protokollschichten hier
implementiert werden. Nach oben zu einer Applikation wird ein Rechner mittels CardBus angeschlossen.
Nach unten, zu einem Bluetooth-Radiomodul mit MAC/
PHY-Implementation wird zur Zeit eine serielle UARTSchnittstelle verwendet. Später wird diese durch einen Anschluss mit 54 Mbps an den IHP-eigenen IEEE
802.11a-Chipset ersetzt werden.
For this purpose, the project developed a special chip.
The system architecture is shown in Fig. 2. Since the
middle layers of the protocol stack are implemented
here, both an upper interface (to an application) and a
lower interface (to a radio modem with the MAC/PHY
layers) are needed. A CardBus interface connects a
host computer to the chip. For the lower interface, a
serial (UART) connection to an external Bluetooth module is currently being used. Later, a high-speed connection to the IHP-developed IEEE 802.11a chipset will
allow data rates of up to 54 Mbps.
CardBus (Linux Host)
CardBus
(Master)
ISPRAM
(32 kB)
EC
AMBA-AHB
UART 0
(Master)
DSPRAM
(8 kB )
APB
Serial 1+2
GPIO
MIPS
Processor
Core
Bridge
EJTAG
Bridge
(Master)
UART 1+2
GPIO
External
Memory
Memory Controller
(AHB Slave))
Flash
SI Bus
Registers
&
Control
Check
Sum1
SRAM
Check
Sum2
SRAM (32 kB)
AES
Serial 0 (Bluetooth RF Module)
Abb. 2:
Fig. 2:
Die Systemarchitektur des TCP/IP-Chips.
The system architecture of the TCP/IP chip.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
31
Ausgewählte Projekte
Drahtloses Internet
Bluetooth
Module
TCP1 – Chip
CardBus
connector
JTAG
Connector
UART
JPIO
Diagnostic
Select
Selected Projects
Wireless Internet
Diagnostic LEDs
Abb. 3:
Fig. 3:
Der TCP/IP-Chip als Teil eines PC-Cardsystems.
The TCP/IP chip as part of a PC-Card system.
Der Chip basiert auf einem integrierten MIPS-Prozessor und einem AMBA-Systembus. Zwei besondere Maßnahmen reduzieren die Last auf den Prozessor und
sparen somit Energie. Erstens wird die TCP-Prüfsumme in Hardware ausgeführt, wobei der Einsatz von
zwei identischen Einheiten die parallele Verarbeitung
von Daten über beide Schnittstellen erlaubt. Zweitens
kopieren beide Schnittstellen ihre Daten zu oder von
dem internen Speicher, ohne dass der Prozessor daran
beteiligt ist. Damit werden alle Operationen, die die
Daten direkt anfassen, in Hardware behandelt. Dem
Prozessor bleiben vergleichsweise komplizierte aber
weniger rechenintensive Aufgaben wie die Behandlung
der TCP/IP-Header und der Verbindungsauf- und abbau. Untersuchungen an unserer TCP/IP-Implementierung haben gezeigt, dass 80% bis 90% der Energie bei
diesen Schritten verbraucht wird.
Der Chip wurde auch dazu entworfen, andere Entwicklungen im IHP aufzunehmen oder zu unterstützen. Ein
AES-Modul aus dem Projekt Mobile Business Engine
erlaubt die Verschlüsselung der übertragenen Daten.
Zusätzliche periphere Schnittstellen (GPIO, UART) erlauben es, den Chip zur Entwicklung von Sensorchips
einzusetzen. Zur Zeit wird der Chip als PC-Card getestet (Abb. 3).
32
The chip is based on a MIPS processor core and an
AMBA bus. To reduce the load on the processor and
to save power, two features were implemented. Firstly, the TCP checksum is done using special hardware
blocks. Two such blocks were implemented to allow
parallel processing of data over both interfaces. Secondly, data can be copied to and from the internal
SRAM directly from the upper and lower interfaces.
This way, all operations which run directly over the
payload of the TCP packets are handled by hardware.
The processor is left with comparatively complicated
but low-effort tasks, such as construction or evaluation of the TCP/IP headers, the algorithms for TCP
congestion control, and connection buildup and teardown. Profiling of our own TCP/IP program has shown
that 80% to 90% of the power is consumed here.
The chip was also designed to support other applications within the IHP. An AES encryption module from
the Mobile Business Engine project was included to allow on-the-fly encryption of data payloads. Additional
external interfaces (GPIO, UART) make it possible to
test sensor network applications. The chip is currently
being evaluated on a PC-Card test board (Fig. 3).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
Link-Emulator für das
IEEE 802.11a MAC Protokoll
Link Emulator for the
IEEE 802.11a MAC Protocol
Der Link-Emulator implementiert das Medium-AccessControl (MAC) -Protokoll des Standards IEEE 802.11a
für ein drahtloses LAN auf einer PC-Steckkarte. Mehrere MAC-Module können mittels eines programmierbaren
Logik-Bausteins zu einem 802.11-Netzwerk verknüpft
werden. Der Logik-Baustein emuliert die physikalische
Übertragungsschicht und erlaubt eine gezielte Steuerung ihres Übertragungsverhaltens. Ein solches System kann zur Entwicklung spezieller Erweiterungen
des IEEE 802.11-MAC- oder PHY-Protokolls benutzt
werden.
The link emulator implements the Medium Access Control (MAC) protocol of the IEEE 802.11a wireless LAN
standard on a plug-in PC card. Several MAC modules
can be connected by a programmable logic device
emulating the physical layer to form an 802.11 network. The PHY emulator allows for control of many
PHY layer and channel properties. Such a system may
be used as a development tool for special extensions
of the IEEE 802.11a MAC or physical layers.
Der Link-Emulator des IHP dient als Zwischenstufe bei
der Entwicklung eines IEEE 802.11a-Modems im Rahmen des von der Europäischen Union geförderten Projektes WINDECT (http://www.windect.ethz.ch). Dessen
Ziel ist es, Möglichkeiten für Telefonie über ein drahtloses LAN zu untersuchen und zu demonstrieren. Im
Unterschied zu Voice-over-IP (VoIP) wird in WINDECT
eine priorisierte HCCA-Verbindung des IEEE 802.11Protokolls für den Telefonkanal benutzt. Dies garantiert die erforderliche Qualität des Dienstes (QoS), wobei soviel Übertragungskapazität wie möglich für den
niedrig priorisierten Datentransfer des LAN verbleibt.
CardBus
connector
Abb. 4:
Fig. 4:
IHP’s MACChip
1 Mbyte
RAM
IHP’s link emulator serves as an intermediate step in
the development of an enhanced IEEE 802.11a modem
for the WINDECT project, funded by the European Commission (http://www.windect.ethz.ch). The goal of this
project is to investigate and demonstrate high-quality
telephony over a wireless LAN, i.e. to unify wireless
voice and data networks using only one infrastructure. In contrast to voice-over-IP (VoIP), WINDECT implements the voice stream as a prioritized HCCA connection in an IEEE 802.11a system. This guarantees the
required quality of service (QoS) in bandwidth and latency for the telephony channel, leaving as much bandwidth as possible for unprioritized LAN data transfer.
8 Mbyte
flash
EJTAG + UART
prog. interfaces
EPP connector to
PHY emulator
Foto des MAC-Moduls eines Link-Emulators für IEEE 802.11a.
Photo of the MAC module of the IEEE 802.11a link emulator.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
33
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
Das MAC-Protokoll ist als Hardware-Software CoDesign auf der Basis eines MIPS-4kEp-Prozessors mit
integiertem Hardware-Accelerator für zeitkritische Funktionen realisiert. Der Emulator für die physikalische
Übertragungsschicht wird über eine Parallel-Schnittstelle (EPP) angeschlossen. Als Schnittstelle zu den
höheren Protokollschichten stehen CardBus oder PCMCIA zur Verfügung. Der MAC-Prozessor-Chip wurde in
der 0,25-µm-CMOS-Technologie des IHP hergestellt.
Ein komplettes MAC-Modul, d.h. Prozessor, Speicher
und Peripherie, passt auf eine Standard PC-Karte und
kann in Notebook, PC oder PDA verwendet werden
(Abb. 4). Ein Link-Emulator-System wurde mit grossem
Erfolg bei der Entwicklung des Kommunikationssystems für das Projekt WINDECT verwendet.
The MAC protocol is implemented as a hardware-software co-design on the basis of a MIPS 4kEp processor
with attached hardware accelerator for time-critical
protocol functions. The PHY layer emulator is connected via an enhanced parallel port (EPP). Either CardBus or PCMCIA may be used as an interface to higher
layers. A MAC chip consisting of the MIPS core with
integrated hardware accelerator and interfaces was fabricated using IHP’s 0.25 µm CMOS technology. A complete MAC unit, i.e. processor, external RAM, flash and
peripherals fits on a standard PC card, which can be
plugged into a notebook or PDA computer (Fig. 4).
The link emulator system was successfully employed
during the development of the WINDECT communication system.
Abb. 5 zeigt die nächste Entwicklungsstufe der Arbeiten für das WINDECT Projekt: das Test Board für ein
komplettes, IEEE 802.11a kompatibles, 5-GHz-WLANModem. Es besteht aus dem MAC-Prozessor, der auch
im Link-Emulator benutzt wird, jedoch erweitert um einen PHY Layer mit digitalem Basisband-Prozessor und
5-GHz-Analog-Front-End.
Fig. 5 presents the next development stage within
the WINDECT project – a test board for a complete
5 GHz WLAN Modem complying with the IEEE 802.11a
standard. It consists of the same MAC processor as
used with the Link Emulator, but extended with a real
PHY layer having the main components Digital Baseband Processor and 5 GHz Analog Front End.
CardBus
connector
Abb. 5:
Fig. 5:
34
IHP’s MAC-Chip
RAM + Flash
IHP´s Digital
Baseband Chip
Baseband
FPGA
Foto des Test Boards für ein IEEE 802.11a-WLAN-Modem.
Photo of the IEEE 802.11a WLAN Modem Test Board.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
IHP´s Analog
Front End Chip
Antenna
Connector
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
Infrastruktur für Funktionaltest/Functional Test Infrastructure:
Agilent SOC93000 Testsystem (links/left)
Accretech UF200 Wafer Prober (rechts/right)
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
35
Ausgewählte Projekte
Drahtloses Internet
Selected Projects
Wireless Internet
Integrierte Schaltkreise für
60-GHz-Anwendungen
Integrated Circuits for
60 GHz-Applications
Es werden integrierte Schaltkreise für die drahtlose
Kommunikation bei 60 GHz entwickelt.
Integrated circuits for wireless communications at
60 GHz are developed.
Das unlizensierte 60-GHz-Band von 57 bis 64 GHz ermöglicht Kommunikation mit hohen Datenraten. Angestrebte Anwendungen sind drahtlose Netzwerke sowie
Punkt-zu-Punkt Kommunikation.
The unlicensed 60 GHz band from 57 to 64 GHz enables high-data-rate communications. Target applications are wireless networks and point-to-point communication.
Silizium-Germanium-Technologie mit Transitfrequenzen
über 200 GHz ist perfekt geeignet, um Technologien
basierend auf Verbindungshalbleitern auf dem Gebiet
der Millimeterwellenkommunikation zu ersetzen. Diese
Technologie bietet eine hohe Integrationsdichte bei niedrigen Kosten. Eine vielversprechende Anwendung stellt
die drahtlose Kommunikation in dem 60-GHz-ISM-Band
dar. Der vorhandene IEEE 802.11a-WLAN-Standard gestattet drahtlose Kommunikation in dem 5-GHz-Band
basierend auf OFDM bei moderaten Datenraten unter
schwierigen Kanalbedingungen. Die Kombination eines
60-GHz-OFDM-Systems für hohe Datenraten mit 802.11a
würde eine perfekte Lösung für eine Vielfalt von Anwendungsszenarien darstellen. Kompatibilität eines 60-GHzOFDM-Systems mit 802.11a ist deshalb zwingend erforderlich. Dies gestattet ferner die Wiederverwendung der
Schaltkreise, welche für 5 GHz entwickelt wurden.
Silicon-Germanium BiCMOS technology with transit frequencies above 200 GHz is perfectly suited to replace
compound semiconductor technologies in the field of
millimeter-wave communication systems. This technology offers high integration at low cost. Wireless communication in the 60 GHz industrial, scientific, medical (ISM) band represents a promising application.
The existing IEEE 802.11a standard for WLAN allows
wireless communication in the 5 GHz band based on
OFDM with moderate data rates under difficult channel conditions. The combination of a 60 GHz high data
rate OFDM-system and 802.11a would represent a perfect solution for a wide range of application scenarios. Compatibility of a 60 GHz-system with 802.11a
is, therefore, mandatory. It also allows the circuitry
developed for 5 GHz to be re-used.
20
S21 simulated
S21 measuread
Noise Figure simulated
Noise Figure minimum
S - Parameters (dB)
10
0
S22 simulated
S22 measured
-10
S11 simulated
S11 measured
-20
-30
30
40
50
60
70
80
90
Frequency (GHz)
Abb. 6:
Fig. 6:
36
Gemessene Verstärkung und Reflexion eines 60-GHz-LNA.
Measured gain and reflection of 60 GHz LNA.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Ausgewählte Projekte
Drahtloses Internet
Es wurde ein Frequenzplan erdacht, der es gestattet,
das Frequenzband von 60 GHz bis 61 GHz auf eine
Frequenz von etwa 5 GHz herunterzumischen, um ein
OFDM-System kompatibel zum IEEE Standard 802.11a
zu ermöglichen. Dies erfordert einen rauscharmen Verstärker (LNA) für 60 GHz, einen Mischer und einen
spannungsgesteuerten Oszillator (VCO) eingebettet
in eine Phase-locked Loop (PLL), um eine stabile Frequenz von 56 GHz zu generieren. Abb. 6 zeigt die Verstärkung und die Rückwärtsisolation eines integrierten
LNA in SiGe:C-BiCMOS-Technologie. Abb. 7 zeigt ein
Chipfoto einer vollintegrierten PLL mit einem gemessenen Durchstimmbereich von 3,3 GHz. Das Ausgangsspektrum dieser PLL ist in Abb. 8 dargestellt.
Selected Projects
Wireless Internet
A frequency plan was conceived, which allows to convert the frequency band from 60 GHz to 61 GHz to
a frequency around 5 GHz to enable an OFDM system compatible to the IEEE 802.11a standard. This requires a low-noise amplifier (LNA) for 60 GHz, a downconversion mixer and a voltage-controlled oscillator
(VCO) embedded in a phase-locked loop (PLL) to generate a stable frequency of 56 GHz. Fig. 6 shows the
gain and the reverse isolation of an integrated LNA in
SiGe:C BiCMOS technology. Fig. 7 shows a chip photo of a fully integrated PLL with a measured tuning
range of 3.3 GHz. The output spectrum of this PLL is
shown in Fig. 8.
Delta 2 [T1]
Ref Lv 1
-10 dBm
-12.98 dB
200.000 000 00 KHz
RBW
VBW
SWT
-10
1 [T1]
-15
1 [T1]
1
-20
-25
30 KHz
30 KHz
5 ms
2 [T1]
#6
Unit
-22.96
57.34400892
-12.98
200.00000000
-12.44
-200.00000000
dBm
dBm
GHz
dB
KHz
dB
KHz
A
SGL
1 SA
1 AVG
-30
1
2
-35
MIX
-40
-45
-50
-55
-60
Abb. 7:
Fig. 7:
Chip-Foto einer vollintegrierten 56-GHz-PLL.
Chip photo of fully integrated 56 GHz PLL.
Center 57.34403892 GHz
150 KHz
Date:
11:17:54
Abb. 8:
Fig. 8:
01.Nov.2004
Span 1.5 MHz
Hochaufgelöstes Ausgangsspektrum einer 56-GHz-PLL.
High-resolution output spectrum of 56 GHz PLL.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
37
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Technologieplattform/
Technology Platform
Hochgeschwindigkeits-Bipolartransistoren
High-Speed Bipolar Transistors
Ziel des Projektes ist die Verbesserung der maximalen Leistungsfähigkeit von Hochgeschwindigkeits-npnbzw. pnp-SiGe:C-HBTs.
Target of this project is to improve the maximum performance of high speed npn and pnp SiGe:C HBTs, respectively.
Auch im höchsten Leistungsniveau wird für SiGe:CHBTs ein selektiv implantierter Kollektor verwendet,
um eine lokal verstärkte Kollektordotierung zu formen, die sowohl die Basis-Kollektor-Laufzeit als auch
die externe Basis-Kollektor-Kapazität reduziert. Trotz
dieser Maßnahme verbrauchen konventionelle Kollektor-Anordnungen mehr Si-Fläche als nötig ist, um einen
widerstandsarmen Strompfad vom aktiven Transistor
zum externen Kollektorgebiet zu bilden.
Including the highest performance level, a selectivelyimplanted collector is used for SiGe:C HBTs to provide a locally enhanced collector doping, reducing both
the base-collector transit time and the external basecollector capacitance. However, conventional collector designs consume more Si area than it is needed
to form a low resistance current path from the active
transistor to the external collector region.
Wir entwickelten ein neues Kollektormodul, das die parasitäre Basis-Kollektor-Kapazität substanziell reduziert.
Dies wurde durch Aushöhlen des Kollektorgebietes erreicht. Abb. 9 zeigt die neue Kollektorstruktur in einem
TEM-Querschnittsbild im Vergleich mit einer schematischen Darstellung.
Emitter
We developed a new collector module, that substantially reduces parasitic base-collector capacitances.
This was achieved by an undercut of the collector region. Fig. 9 shows the novel collector structure as
TEM cross-section in comparison with a schematic
drawing.
Emitter
SiGe Base
Base Poly
STI
Abb. 9:
Fig. 9:
38
SiGe Base
Collector
Pedestal
Querschnitt der fertigen HBT-Struktur in schematischer
Darstellung (links) und als TEM-Bild (rechts).
Cross-sections of the final HBT structure as a schematic
drawing (left) and a TEM image (right).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Base Poly
Ausgewählte Projekte
Technologieplattform
Im Gegensatz zu konventionellen Konstruktionen besitzt die externe, dielektrisch isolierte Basisschicht
einen einkristallinen Abschnitt auf dem Isolationsgebiet. Dadurch wird es möglich, durch die Variation der
Kollektorfensterweite bezüglich des Emitterfensters
die HF-Leistungsfähigkeit zu optimieren, wobei man
weitgehend befreit ist von der Sorge um erhöhte Leckströme an einer Facette oder einen vergrößerten Basiswiderstand.
Durch Invertierung der Dotierungstypen sind auf verschiedenen Scheiben npn- und pnp-HBTs mit dem gleichen Prozessablauf hergestellt worden. Sowohl für
npn- als auch für pnp-SiGe:C-HBTs konnten wir f T-Werte und CML-Gatterverzögerungszeiten (Abb. 10) demonstrieren, die die bis dahin veröffentlichten Bestwerte ihrer Klasse übertrafen.
IJ (ps)
10
5
pnp
Selected Projects
Technology Platform
In contrast to conventional constructions, the external, dielectrically-isolated base layer has a single crystaline part on the isolation region. This allows us to
optimize the RF performance by varying the collector
window enclosure of the emitter window largely relieved of concerns arising from facet leakage or increasing base resistance.
On different wafers, npn and pnp transistors were produced in the same flow by inverting the doping types.
For both npn and pnp SiGe:C HBTs, we demonstrated
peak f T values and CML gate delays (Fig. 10) that surpassed the best in class data had been reported till
then.
§V=300mV
5.9 ps
AE = 0.175 x 0.84 µm2
IHP 2003
npn
3.2 ps
AE = 0.175 x 0.42 µm2
1
Current per Gate (mA)
10
Abb. 10: CML-Ringoszillator-Gatter-Verzögerungszeit IJ über Strom
pro Gate für Oszillatoren bestehend aus 53 Stufen mit
npn- bzw. pnp-SiGe:C-HBTs. T=300 K, |VEE|=2,5 V, differentieller Spannungshub 300 mV.
Fig. 10: CML ring oscillator gate delay IJ vs. current per gate for
oscillators consisting of 53 stages with npn and pnp
SiGe:C HBTs, respectively. T=300 K, |VEE|=2.5 V, differential voltage swing 300 mV.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
39
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Integration von Hochgeschwindigkeits-SiGe:C-HBTs mit DünnfilmSOI-CMOS
Integration of High-Speed SiGe:C
HBTs with Thin-Film SOI CMOS
Das Ziel des Projektes war die Entwicklung eines Verfahrens zur Integration schneller SiGe:C-Heterobipolartransistoren (HBTs) mit modernen CMOS-Technologien
auf SOI-Substraten (Silicon on Insulator).
The goal of the project was to demonstrate a way
to integrate high-speed SiGe:C heterojunction bipolar
transistors (HBTs) with a complementary metal-oxidesemiconductor (CMOS) technology on thin-film siliconon-insulator (SOI) wafers.
Die Integration von SiGe:C-HBTs für Hochfrequenzanwendungen mit SOI-CMOS-Technologien ist ein vielversprechender Ansatz zur Realisierung von Systemlösungen für die Telekommunikation auf einem Siliziumchip
(System-on-Chip). Das SOI-Substrat kann zur Verbesserung der Eigenschaften der CMOS-Feldeffekttransistoren und der passiven Schaltungskomponenten sowie
zur verbesserten Isolation genutzt werden. Skalierte
SOI-CMOS-Technologien erlauben die Realisierung einer steigenden Anzahl von Schaltungsfunktionen im
Radiofrequenzbereich.
Für viele Anwendungen im mm-Wellenbereich und für
Kommunikationssysteme mit großer Bandbreite bleiben jedoch Hochgeschwindigkeits-HBTs wegen ihrer größeren Spannungsfestigkeit, ihres großen Ausgangswiderstandes, ihres geringen 1/f-Rauschens und
der großen Zahl erprobter Schaltungskonzepte unverzichtbar.
The integration of high-speed SiGe:C HBTs with stateof-the-art SOI CMOS technologies is a promising route
to system-on-chip (SoC) applications for telecommunications. The SOI substrate can be used to enhance
the performance of MOS transistors and on-chip passive circuit components, and to minimize isolation problems. Scaled SOI CMOS technologies can facilitate
the implementation of an increasing number of radiofrequency (RF) functions.
However, high-speed HBTs remain indispensable for
many mm-wave applications and high-bandwidth communication systems due to their high voltage capability, high output resistance, low 1/f noise, and the large
number of proven RF circuit concepts.
250
VCE =1.5 V
f T, f max (GHz)
200
150
100
f max
fT
50
0
10 -5
AE =2x (0.21 x 0.84)µm2
10 -4
10 -3
10 -2
Collector Current (A)
Abb. 11:
Fig. 11:
40
REM-Querschnitt eines HBTs auf SOI-Substrat. Die hochleitende Kollektor-Wanne wird im Silizium-Substrat
unterhalb der vergrabenen Oxidschicht gebildet.
SEM cross section of an HBT on SOI substrate. The highly
conductive collector well is formed in the Si substrate
below the buried oxide.
Abb. 12: Transitfrequenz f T und maximale Oszillationsfrequenz
f max in Abhängigkeit vom Kollektorstrom.
Fig. 12: Transit frequency f T and maximum oscillation frequency
f max vs. collector current.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Ausgewählte Projekte
Technologieplattform
Es wurde ein neues Integrationsverfahren für Hochgeschwindigkeits-SiGe:C-HBTs auf SOI-Substraten entwickelt. Im Gegensatz zu allen bisherigen Ansätzen
ist die Leistungsfähigkeit der SiGe:C-HBTs nicht durch
die geringe Silizium-Schichtdicke der CMOS-kompatiblen SOI-Substrate begrenzt. Die entscheidende Neuerung des entwickelten Verfahrens besteht in der Realisierung eines Kollektors mit geringem Widerstand in
dem Si-Substrat unterhalb der Oxidschicht. Die HBTs
werden in Fenstern in der Oxidschicht gefertigt, die
durch selektive Siliziumepitaxie gefüllt sind (Abb. 11
und 12).
SiGe:C-HBTs mit Grenzfrequenzen f T = 220 GHz und
f max = 230 GHz wurden realisiert (Abb. 13). Das sind
die schnellsten bisher gezeigten HBTs auf CMOS-kompatiblen SOI-Substraten. Die HBTs wurden mit vollständig verarmten SOI-CMOS-Transistoren mit 90 nm Gatelänge und 25 nm Silizium-Schichtdicke integriert.
A new integration scheme for high-speed SiGe:C HBTs
on SOI substrates was developed. In contrast to all
previous approaches, the HBT performance is not
limited by the small silicon thickness of the CMOScompatible SOI substrates. The key new process feature is the formation of low-resistive collectors in the
silicon substrate below the buried oxide of the SOI
wafer. The HBTs are fabricated in windows of the buried oxide which are filled by selective silicon epitaxy
(Figs. 11 and 12).
SiGe:C HBTs with f T/f max values of 220 GHz/230 GHz
were achieved (Fig. 13). These are the fastest reported HBTs on CMOS-compatible SOI substrates. The
HBTs were integrated with fully-depleted CMOS transistors with 90 nm gate length and 25 nm silicon thickness.
MOSFET
HBT
B
Selected Projects
Technology Platform
E
C
S
D
SiGe:C base
Buried Oxide
Collector
Si substrate
Abb. 13:
Schematischer Querschnitt eines auf einem SOI-Wafer
integrierten HBT und MOSFET.
Fig. 13:
Schematic cross section of an HBT and a MOSFET integrated on a silicon-on-insulator wafer.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
41
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Kostengünstiger, modularer
BiCMOS-Prozess für HF-SoC
Low-cost, Modular BiCMOS Process
for RF-SoCs
Ziel dieses Projektes ist die Entwicklung und Qualifizierung eines kostengünstigen, modularen 0,25-µmSiGe:C-BiCMOS-Prozesses, der die Herstellung von
Ein-Chip-Systemen mit digitaler, analoger, gemischter
und HF-Signalverarbeitung (HF-SoC) erlaubt.
The aim of this project is the development and qualifi cation of a cost-optimized, modular 0.25 µm SiGe:C
BiCMOS platform suitable for the fabrication of systems on-a chip with digital, analog, mixed-signal and
RF functionality (RF-SoCs).
SiGe:C-BiCMOS wird gegenwärtig als eine der Technologien angesehen, die sich zur Herstellung von HF-SoC
am besten eignen. Sie erlaubt es, modernste CMOSSchaltungen mit bester (bipolarer) HF-Performance auf
einem Chip zu kombinieren. Außerdem kann die dringende Forderung des Schaltungs- und Systementwurfs
nach Verfügbarkeit weiterer Funktionen, wie Hochvolt
(LDMOS) oder nichtflüchtiger Speicherung (NVM),
ohne ernsthafte Integrationsprobleme erfüllt werden.
Die größte Herausforderung bei der Entwicklung solcher SoC-Plattformen ist aber die Findung eines vernünftigen Kompromisses zwischen Kosten und offeriertem Bauelemente-Spektrum sowie -Parametern.
SiGe:C BiCMOS is currently considered to be one of
the technologies of choice for the fabrication of RFSoCs because it allows the combination of state-ofthe-art CMOS circuitry with best (bipolar) RF performance on a single chip. Moreover, the urgent demand
from circuit and system design for the modular integration of further functions, such as high-voltage
(LDMOS) or non-volatile memory (NVM), can be fulfilled
without serious integration issues. However, the biggest
challenge for the development of SoC platforms is to
compromise device performance and functionality on the
one hand, with cost, given by features such as the number of mask and process steps, yield etc., on the other.
RF-CMOS Flow
VD Modules
Shallow Trench Isolation
Well Implants
Gate Oxidation
Gate Poly Deposition
HBT - Module
Gate Structuring
Gate Spacer Formation
Salicide Blocker
Contact Module
Complementary
LDMOS Module
Module
BEOL including:
4 Al Layers (2 µm thick upper layer)
MIM Module
Abb. 14:
Fig. 14:
Mask no.
RF-CMOS
(qualified)
SGB25VD-Prozessablauf.
SGB25VD process flow.
Im IHP wurde der Prozeß SGB25VD entwickelt, eine kostengünstige BiCMOS-Plattform für HF-SoC-Anwendungen.
Der Prozess kombiniert ein 0,25-µm-HF-CMOS-Gerüst
mit einem 1-Masken SiGe:C-HBT-Modul und einem komplementären, 2-Masken LDMOS-Modul. Abb. 14 zeigt ein
Schema des Prozessablaufs und Tabelle 2 die wichtigsten aktiven und passiven Bauelemente, deren Fabrikation insgesamt nur 21 Maskenschritte erfordert.
Die in den Abb. 15 bzw. 16 gezeigten Ausbeutedaten
belegen die CMOS-VLSI- und Bipolar-MSI-Tauglichkeit
42
IHP has developed the process SGB25VD, a low-cost
modular SiGe:C BiCMOS platform for RF-SoC applications. It combines a 0.25 µm RF-CMOS backbone with
a one-mask SiGe:C HBT module and a two-mask complementary LDMOS module. Fig. 14 shows a SGB25VD
process flow schematic, while table 2 summarizes the
essential active and passive devices fabricated by the
process using only 21 mask steps in total.
HBT
(qualified)
LDMOS
(under
qualification)
18
Devices
nMOS transistors
pMOS transistors
Isol. nMOS transistors
MOS varactor
(3.2:1 tuning range)
Junction varactor
Several poly resistors
(6 Ý, 210 Ý, 310 Ý, 2 kÝ)
MIM cap (1fF/µm2)
Predefined inductors
1
80 GHz f T/ 2.4 V BVCEO
50 GHz f T/ 3.8 V BVCEO
30 GHz f T/ 7 V BVCEO
2
nLDMOS
pLDMOS
Isolated nLDMOS
Tabelle 2: Wesentliche SGB25VD-Bauelemente.
Table 2: SGB25VD device summary.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
100
Bit Error Count = 0 (@ 1.2-3.2V)
80
60
40 A B C D E F G
20
CMOS
H
I
J
K
L
M
BiCMOS lots
Yield of HBT-Arrays (%)
1M-SRAM Wafer Yield (%)
Ausgewählte Projekte
Technologieplattform
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Technology Platform
100
80
60
40 50 GHz HBT
vs. 80 GHz HBT
vs. 30 GHz HBT
20
0
1
Lot ID (A-M)
2
3 4 5 6
Lot ID (1-10)
only
50 GHz HBT
measured
7
8
9 10
Abb. 15: Ausbeute-Trend für einen 1-Mbit-SRAM.
Fig. 15: Yield trend chart for a 1 Mbit SRAM.
Abb. 16: Ausbeute-Trend für 4-k-HBT-Arrays.
Fig. 16: Yield trend chart for 4 k HBT arrays.
des Prozesses als wesentliche Voraussetzungen für
eine kostengünstige Herstellung von HF-SoC. Einige
Ergebnisse der SGB25VD-Prozeßqualifikation sind in
Abb. 17 (zur intrinsischen HBT-Zuverlässikeit) und Tabelle 3 (CMOS Stress-Tests) wiedergegeben. Die Qualifizierung wesentlicher SGB25VD-Module wurde mittlerweile erfolgreich abgeschlossen. Das erlaubte es
uns, den Prozess auch für externe Kunden, in direkter
Kooperation oder über Europractice, freizugeben.
Weitere Module, wie ein NVM mit niedrigem Energieverbrauch (siehe dazu den Flash-Beitrag in diesem
Heft), ein MIM-Kondensator mit höherer Kapazitätsdichte und ein HBT mit verbesserten HF-Parametern
sind in Entwicklung (Tabelle 4). Der aufgeführte HBT
mit 130 GHz f T bei 2,1 V BVCEO kann dabei zusätzlich
zum Standard-HBT-Portfolio produziert werden.
The CMOS and bipolar yield data shown in the Figs. 15
and 16 respectively demonstrate the CMOS VLSI and
bipolar MSI ability of the process as essential conditions for a cost-effective fabrication of RF-SoCs. Some
results of the SGB25VD process qualification are given
in Fig. 17 (concerning bipolar intrinsic reliability) and
table 3 (CMOS stress tests). Meanwhile, the qualification of the key SGB25VD process modules was successfully completed. It allowed us to release the process not only for IHP designers but also for external
customers, via direct cooperation or Europractice
service. Further modules, such as a low-power NVM
(for more details, see the Flash contribution of this issue), a MIM capacitor with higher cap density, or an
HBT with improved RF parameters are under development (table 4). Note that the feasible, 130 GHz f T, 2.1 V
BVCEO HBT can be fabricated in addition to the standard SGB25VD HBT portfolio.
Tabelle 3: Ergebnisse der 1-Mbit-SRAM-Stress-Tests.
Table 3: 1 Mbit SRAM stress test summary.
Module
Mask no.
Devices
NVM (Flash)
(1M feasibility)
4
Low-power, floating
gate cell memory
MIM capacitor
(feasibility)
0
> 1.5 fF/µm2 cap density
High-f T HBT
(feasibility)
1
130 GHz f T / 2.1 V BVCEO
VCB =1V
107
10 6
11 years
10 5
T=100°C
10 4
IE @f T,max
• HTOL (2.75 V, 125°C, 1 MHz, 1000 hours, 336DUTs)
Test passed with 2/336 fails in different lots
• Static Bake (150°C, 1000 hours, 120 DUTs)
Test passed with 0/120
• AATC (-65°C to 150°C, 1000 cycles, 90 DUTs)
Test passed with 0/90
• Pressure Cooker (121°C, 100% RH, 2 bar, 168 hours, 90 DUTs)
Test passed with 0/90
• EFRS (2.5 V, 125°C, 1 MHz, 48 hours, 1278 DUTs)
0.4% fail (5/1278)
10 8
Lifetime (hours)
Devices from 3 lots
Pass criteria:
continuity test (open, shorts)
stand-by current of all blocks
functionality at 4 different voltages, ...
103
102
101
1
T=150°C
10
Stress Current IE (mA)
100
Abb. 17: Stromabhängigkeit der Lebensdauer (für 10% ß-Degradation @ VBE = 0,7 V) für ein Array mit vier parallelgeschalteten
80-GHz-Transistoren.
Fig. 17: Current dependence of lifetime (for 10% ß-degradation
@ VBE = 0.7 V) for an array of four parallel 80 GHz HBTs.
Tabelle 4: In Entwicklung befindliche Module.
Table 4: Modules under development.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
43
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Integration von Flash-Speicher
Flash Memory Integration
Das Ziel dieses Projektes ist die Demonstration einer kostengünstigen, auf einem Tunnelstrom-Schreibkonzept basierenden Prozesstechnologie zur Integration eines „embedded-Flash“-Halbleiterspeichers in
einen leistungsfähigen 0,25-µm-SiGe:C-HF-BiCMOSProzess.
The goal of this project is the demonstration of a costeffective process technology for integrating an embedded flash memory based on a low power tunnel writing concept into a 0.25 µm, high-performance SiGe:C
RF-BiCMOS process.
Eine modulare Technologie für nichtfl üchtige Speicher,
eingebettet in einen SiGe:C-HF-BiCMOS-Prozess, bietet herausragende Möglichkeiten für eine Reihe wichtiger Anwendungen auf System-Ebene. Die meisten SiFoundries bieten „embedded Flash“-Optionen für ihre
CMOS- und RF-CMOS-Prozesse an. Für SiGe:C-BiCMOS
stellt es somit eine konsequente Weiterentwicklung
dar, die aber noch nicht etabliert ist. Hauptanforderungen sind geringe Kosten und Leistungsverbrauch,
insbesondere zur Verwendung in tragbaren Systemen.
Es werden Speicher kleiner bis mittlerer Dichte benötigt (von einigen Byte, z.B. für nichtflüchtige Register,
bis zu einigen Mbit, z.B. zur Speicherung von Betriebssystemen). Die Zellengröße und Zellenleistungsfähigkeit muss für solche Speicher ausreichen.
Insgesamt liegen die Vorteile eines solchen Speichers
in der zusätzlichen Systemfunktionalität und reduzierten Systemkosten.
Es ist eine Prozesstechnologie zur Integration eines
„embedded-Flash“-Speichers in die 0,25-µm-SiGe:C-HFSoC-Technologieplattform des IHP entwickelt worden.
Aufgrund der CMOS-Kompatibilität ist ein Standard-„Floating-gate“ Ansatz gewählt worden. Als Mechanismus
zur Programmierung der Zelle wurde leistungsarmes
Fowler-Nordheim-Tunneln gewählt. Eine Konsequenz
daraus ist die Anforderung, hohe Spannungen zu handhaben (+/- 6 V), was zusätzliche Hochvoltbauelemente (HV-MOS) erfordert. Die Herausforderung ist, FlashZellen zusammen mit HV-MOS-Bauelementen kostengünstig zu integrieren, d.h. mit wenigen zusätzlichen
Maskenebenen und Prozessschritten.
Der prinzipielle Prozessablauf ist in Abb. 18 zu sehen.
Es werden 4 zusätzliche Masken benötigt. Einzelne Prozessschritte werden sowohl für Flash-Zellen als auch für
HV-MOS- und CMOS-Bauelemente verwendet. Abb. 19
zeigt eine REM-Querschnittsaufnahme einer Speicherzelle. Einzelzellen zeigen Schreibzeiten bis zu 1 µs bei
Programmierung mit Vprg = 16 V (+/- 8 V an Gate bzw.
Well) und einem V T-Fenster von 4 V zwischen program-
44
A modular non-volatile-memory technology embedded
into a SiGe:C RF-BiCMOS process has significant potential for a range of important system-level applications. Most Si-foundries offer optional embedded flash
modules in their CMOS or RF-CMOS processes. For
SiGe:C BiCMOS this is a consistent development which
has not yet been established. Main requirements are
cost-effectiveness and low power consumption, particularly for use in portable systems. Memories are needed ranging from small to medium density (from a few
bytes, e.g. for non-volatile registers, up to a few Mbit,
e.g. for operation system storage). Cell size and performance must be sufficient for these memory sizes.
The overall advantages of such embedded memory
integration are the added system functionality and reduced total system costs.
A process technology was developed to integrate an
embedded Flash memory into IHP’s 0.25 µm SiGe:C
RF-SoC technology platform. For CMOS compatibility
a standard floating-gate approach was chosen. FowlerNordheim tunneling was chosen as a cell-programming
mechanism due to its intrinsic low power consumption. One consequence is the need to handle the high
voltages (+/- 6 V) used for this technique, which in turn
requires high-voltage (HV) devices. One challenge is to
integrate the flash cells together with HV-MOS transistors at low additional cost in terms of mask count and
process steps.
The principle process fl ow is shown in Fig. 18. The
developed fl ow requires 4 additional mask steps on
top of the baseline BiCMOS fl ow while sharing process steps for flash-cells, HV-MOS and CMOS devices.
Fig. 19 shows an SEM cross section view of one memory cell. The single cells show a writing time of as
low as 1µs for programming with Vprg = 16 V (+/-8 V at
gate and well) and a 4 V V T-window between the written and erased state (see Fig. 20). An endurance of
105 write and erase cycles has been demonstrated.
The HV-MOS transistors show a breakdown voltage of
>10 V, which is sufficient for this application.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Shallow Trench Isolation
High energy P-implant
nMOS, pMOS wells
Dual-gate-oxide wet etch
(Mask 1)
5nm CMOS Gate-oxide
Gate poly deposition
Floating-gate and
Flash-PWELL implant
(Mask 2)
1-Mask HBT- Module
Floating-gate etching
and HV-NWELL implant
(Mask 3)
Abb. 19: REM-Querschnittsaufnahme einer Speicherzelle.
Fig. 19: SEM cross-section of a memory cell.
Control-gate etching
and HV n-LDD implant
(Mask 4)
In cooperation with the Technical University of Kiev a
1 Mbit memory was designed as a demonstrator. The
first devices were fabricated and the principle functionality demonstrated, thus showing the feasibility of
the process for memories of this density. A micrograph of the memory is shown in Fig. 21.
Gate structuring
S/D implants
Backend processing
3
+16V
+14V
2
Abb. 18: Prinzipieller Prozessablauf.
Fig. 18: Principle process flow.
+12V
miertem und gelöschtem Zustand (Abb. 20). Eine Datenwechselstabilität von 105 Schreib- und Löschzyklen
ist gezeigt worden. Die HV-MOS Transistoren erreichen
>10 V Durchbruchspannung.
In Kooperation mit der Technischen Universität Kiev
ist ein 1-Mbit-Demonstrator entwickelt worden, dessen prinzipielle Funktion nachgewiesen werden konnte.
Die Anwendbarkeit der entwickelten Technologie für
solche Speicherdichten ist somit gezeigt worden. Ein
Chipfoto des Speichers ist in Abb. 21 zu sehen.
V t (V)
1
-14V
-2
-3
10 -8
-16V
10 -7
10 -6
10 -5
10 -4
10 -3
10 -2
10 -1
Pulse Width (s)
Fig. 20:
Fig. 21:
-12V
-1
Abb. 20:
Abb. 21:
0
Transientes Verhalten der Flash-Zelle für verschiedene
Programmierspannungen.
Transient characteristic of a memory cell for different
programming voltages.
Chipfoto des 1-Mbit-Demonstrators, zusammen mit
einer REM-Draufsicht auf das Speicherarray vor der
Aufbringung der Metallebenen.
Micrograph of the 1 Mbit demonstrator circuit together
with a top view on the memory-array before formation
of the metal interconnect.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
45
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Modellierung passiver Bauelemente
mit ADS Momentum
Passive Modeling with ADS Momentum
Hauptziel ist die Unterstützung zukünftiger Aktivitäten
der Abteilung Circuit Design im Bereich 77 GHz und später im Bereich 120 GHz. ADS Momentum ist eine 2,5-dimensionale elektromagnetische Simulationsumgebung,
die in der Lage ist, das Verhalten von Metallisierungsschichten bei hohen Frequenzen zu berechnen.
The main goal is to support the upcoming activities of
the circuit design department in the 77 GHz range and
the 120 GHz range at a later stage. ADS Momentum is
a 2.5D electromagnetic simulation environment that is
able to predict the behavior of the metallization layers
at high frequencies.
In HF-Schaltkreisen wirken die Metallisierungsschichten nicht nur als leitende Verbindungen, sondern bilden auch Induktivitäten, Transformatoren, Kapazitäten
und Übertragungsleitungen. Diese passiven Strukturen
müssen sorgfältig entworfen werden, um eine korrekte
Funktion der Schaltkreise zu sichern. Mit einem festen
Satz an Komponenten ist der Designer auf bestimmte
Kombinationen begrenzt. Es ist wünschenswert, parametrisierte Elemente zu haben, die an die aktuellen
Bedürfnisse angepasst werden können. Die Designer
werden damit bei der Entwicklung von Schaltkreisen
wesentlich flexibler. Abb. 22 zeigt einige Teststrukturen, die zur Bewertung der Performance von ADS Momentum genutzt werden. Ein Vergleich zwischen Messung und Simulation ist in Abb. 23 dargestellt.
In the RF circuits the metallization layers not only
act as conducting connections but also form inductors, transformers, capacitors and transmission lines.
These passive structures have to be designed carefully to ensure proper functioning of the circuitries. With
a set of fixed components the designer is limited to
certain combinations. It is desirable to have parameterized elements that can be adapted to meet current requirements, thus enabling designers to become much
more flexible in circuit development. Fig. 22 shows
some test structures that are used to evaluate the performance of ADS Momentum. A comparison between
measurement and simulation is shown in Fig. 23.
a)
b)
c)
Abb. 22: Beispiele für Layouts passiver Teststrukturen: a) und b)
Induktivitäten; c) mäanderförmige Leitbahn.
Fig. 22:
Für die Übertragungsleitung wird bis 60 GHz eine gute
Übereinstimmung von Messungen und Simulation erreicht. Alle Induktivitäten werden bis zu ihrer Eigenresonanzfrequenz gut simuliert. Abhängig vom Design
der Induktivität wurde eine gute Übereinstimmung
auch darüber hinaus bis zu 30 GHz erreicht.
Good conformity of measurement and simulation is
achieved for the transmission line up to 60 GHz. All inductors are well simulated up to their self-resonance
frequency. Good conformity was achieved up to a maximum of 30 GHz, depending on the inductor design.
Eine Verbesserung der Simulationsergebnisse bei Frequenzen von 77 GHz und darüber wird durch Anpas46
Example layouts of passive test structures: a) and b)
inductors; c) meandered transmission line.
An improvement of the simulation results at frequencies of 77 GHz and above is expected by trimming the
substrate description file. It specifies the sequence of
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Ausgewählte Projekte
Technologieplattform
sung der Modellierung der Substrateigenschaften erwartet. Sie spezifiziert die Abfolge von Isolatoren und
Metallen, deren Dicke und die physikalischen Eigenschaften jeder dieser Schichten.
insulators and metals, their thicknesses and the physical properties of each of these layers.
The modeling software IC-CAP optimizes the layer
stack. The relative permittivity Ć r of the oxide layers and silicon are tuned to get the best fit between
measurement and simulation. The conductivity of the
silicon substrate is also tuned. Test structures have
to be developed that are particularly sensitive to the
tuned parameters but less sensitive to measurement
issues. Possible solutions are resonant structures,
since frequencies can be measured very well.
0
1
-30
0
MAG(S21) (dB)
PH(S21) (deg)
Der Schichtstapel wird mit Hilfe der Modellierungssoftware IC-CAP optimiert. Die relative Dielektrizitätskonstante Ć r der Oxidschichten und des Siliziums werden
angepasst, um die beste Übereinstimmung zwischen
Messungen und Simulation zu erhalten. Die Leitfähigkeit der Siliziumsubstrate wird ebenfalls angepasst. Es
müssen Teststrukturen entwickelt werden, die besonders empfindlich auf die angepassten Parameter, aber
weniger empfindlich auf Messprobleme reagieren. Da
Frequenzen sehr gut gemessen werden können, sind
resonante Strukturen dafür mögliche Lösungen.
-60
-90
-120
Measurement
Simulation
-150
Selected Projects
Technology Platform
-1
-2
-3
Measurement
Simulation
-4
-5
-180
0
20
40
60
80
100
120
0
20
40
60
80
100
120
Frequency (GHz)
Frequency (GHz)
Abb. 23: Messung und Simulation einer mäanderförmigen Leitbahn.
Fig. 23: Measurement and simulation of a meandered transmission line.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
47
Ausgewählte Projekte
Technologieplattform
Selected Projects
Technology Platform
Pilotlinie
Pilotline
Das IHP betreibt eine Pilotlinie, die sowohl technologische Entwicklungen als auch den Zugriff auf sehr
leistungsfähige und stabile Technologien für interne
und externe Designer ermöglicht.
IHP is running a pilot line, enabling technological developments as well as access to very powerful and
stable technologies for internal and external designers.
Innovationen bei Technologien und Schaltkreisen erfordern eine hohe Stabilität der Prozesslinie sowie kurze
Präparationszeiten bei hoher Qualität und Ausbeute.
Gegenwärtig sind mehrere 0,25-µm-SiGe:C-BiCMOSTechnologien verfügbar. Sie enthalten integrierte HeteroBipolartransistoren mit Grenzfrequenzen bis 220 GHz
und HF-LDMOS-Bauelemente mit Durchbruchspannungen bis zu 26 V, einschließlich komplementärer Bauelemente. Die Technologien sind im Kapitel „Angebote
und Leistungen“ dieses Berichtes genauer beschrieben. Eine 0,13-µm-BiCMOS-Technologie wird derzeit
entwickelt.
Neben der Nutzung für Schaltkreis- und Systementwicklungen am IHP werden die Technologien als MPW
und Prototyping Service auch externen Partnern und
Kunden angeboten.
Die Steuerung in der Pilot Linie basiert auf einem vollständig automatisierten System. Alle wesentlichen
Prozessdaten werden in einer Datenbank bereitge-
Innovations in technologies and circuits need high pilot line stability as well as short preparation times of
high quality and yield.
There are currently several 0.25 µm SiGe:C BiCMOS
technologies available. They offer integrated HBTs with
cut-off frequencies of up to 220 GHz and RF LDMOS
devices with breakdown voltages up to 26 V, including
complementary devices. The technologies are described in more detail in the chapter "Deliverables and Services" of this report. A 0.13 µm BiCMOS-technology is
currently under development.
In addition to the use for the development of circuits
and systems at the IHP, the technologies are offered
as MPW and Prototyping service to external partners
and customers.
The workflow in the pilot line is managed by a fully automated Manufacturing Execution System. All required
data from WIP (work in process) are stored in a database (Fig. 24). These data are available for management and customers.
The pilot line guarantees a stable yield, typically about
70% for 1 Mbit-SRAMs.
For expedited lots, cycle times can be improved to a
flow factor of 1.4. The flow factor is defined as the actual processing time divided by the minimum possible
processing time for full BiCMOS flows.
The high quality of the pilot line is documented by
the annual reservice of the ISO9001:2000 certification of all technology departments without deviations
(Fig. 25).
Please come and visit our cleanroom.
Abb. 24: Schema des Systems zur Prozess-Steuerung.
Fig. 24: Schematic of the Manufacturing Execution System.
48
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
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Selected Projects
Technology Platform
stellt, auf die sowohl das Management als auch die
Nutzer Zugriff haben (Abb. 24).
Die Pilotlinie garantiert eine stabile Ausbeute, z.B. ca.
70% für einen 1-Mbit-SRAM.
Für priorisierte Lose wird eine Durchlaufzeit erreicht,
die sich lediglich um den Faktor 1,4 von der physikalischen Prozesszeit unterscheidet.
Die hohe Qualität der Pilotlinie wird durch die jährliche
erfolgreiche ISO-Zertifizierung 9001:2000 dokumentiert (Abb. 25).
Gern laden wir Sie zu einer Besichtigung unseres Reinraumes ein.
Abb. 25: DIN EN ISO9001:2000-Zertifikat der DQS GmbH.
Fig. 25: DIN EN ISO9001:2000 certificate from the German DQS
society.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
49
Ausgewählte Projekte
Mater ialien
Selected Projects
Mater ial s
Materialien für die Mikroelektronik/
Materials for Microelectronics
Praseodymsilikat als Zwischenschicht und Gate-Dielektrikum
Praseodymium Silicate as Interface
Layer and Gate Dielectric
Das IHP konzentriert sich bei der Suche nach neuen
Isolatoren hoher Dielektrizitätskonstante für mikroelektronische Anwendungen auf praseodym-basierte Materialien. Dieser Artikel befasst sich mit durch
Festphasenreaktion hergestelltem Praseodymsilikat
als Zwischenschicht und Gate-Dielektrikum.
In the search for new high-k isolators for microelectronic applications IHP concentrates on praseodymiumbased materials. In this article praseodymium silicate,
produced by solid-state reaction, is investigated.
Die untersuchten Schichtstapel wurden durch Verdampfen von metallischem Pr auf einer 1,8 nm dicken
SiO2-Schicht hergestellt. Anschließend erfolgte eine
Luftoxydation und eine Temperung in N2-Atmosphäre
(Abb. 26). Die chemische Zusammensetzung und die
Mikrostruktur wurden analysiert und durch Ab-initioBerechnungen simuliert. Die Ergebnisse zeigen, dass
die Pr-Abscheidung bei Raumtemperatur (RT) zu einer
Bildung von Pr-Silizid und Pr-Oxiden führt. Die Oxidation der Struktur mit nachfolgender Temperung führt
zu einem Stapel aus einem SiO2-basierten Puffer mit
erhöhter Dielektrizitätskonstante und einer Pr-Silikatschicht mit hohem k-Wert.
The stacks under investigation were prepared by evaporating metallic Pr onto 1.8 nm SiO2 fi lm. This was
followed by oxidation in air ambient and annealing in
N2 atmosphere (Fig. 26). The chemical composition
and microstructure was analysed and simulated by ab
initio simulations. The results indicate that Pr deposition at room temperature (RT) leads to the formation
of a Pr silicide and a Pr oxide. The oxidation of the reacted structures, followed by annealing, results in a stacked dielectric composed of a SiO2-based buffer with
an enhanced permittivity and a Pr silicate fi lm with a
high dielectric constant. The leakage current density of
10 -4 A/cm2 was measured for the stacks with an equivalent oxide thickness (EOT) of 1.5 nm. The capacitance voltage traces exhibit a large flatband voltage
Pr
SiO2 / Si-O-N
(Pr 2O3)(SiO) x (SiO2) y /PrSiON
Si (001)
Si (001)
Die Leckstromdichte des Stapels beträgt 10 -4 A/cm2
bei einer äquivalenten Oxidschichtdicke (EOT) von
1,5 nm. Die Kapazitäts-Spannungskurven zeigen eine
große Verschiebung der Flachbandspannung (V FB ).
Diese Verschiebung deutet auf die Anwesenheit von
positiven Ladungsträgern im Stapel hin. Durch den
Austausch von Aluminium durch Gold als Elektrodenmaterial wird V FB signifi kant um den Betrag von 1,3 V
verkleinert. Das ist viel mehr, als man von der Differenz der Austrittsarbeiten von Al und Au (~0.9 V) erwarten würde. V FB ist somit stark von der Gate-Grenzschicht beeinflusst.
Um die elektrischen Eigenschaften des Pr-Silikat/
Si(001) -Systems zu optimieren, wurde eine Technik
zur Verbesserung der Grenzschicht entwickelt. 1 nm Ti
50
Abb. 26: Schematische Darstellung der Festphasenreaktion zwischen
SiO2 /Si-O-N und metallischem Pr.
Fig. 26: Schematic representation of the solid-state reaction between SiO2 /Si-O-N and metallic Pr.
(V FB ) shift, indicating the presence of a positive charge in the stack. Switching away from Al contacts to Au
gate electrodes introduces a signifi cant reduction of
V FB by 1.3 V, which is much more than the change expected from the work function difference between Al
and Au (~ 0.9 V). This is strongly affected by the gate
interface.
To optimize the electrical properties of the Pr silicate/
Si(001) system, we have adopted an interface-engineering approach. 1 nm Ti was deposited at RT in an ultrahigh vacuum (UHV) through electron beam evapora-
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
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Mater ialien
La silicate (Watanabe, Appl. Phys. Lett. 83, 3546(2003))
Hf silicate (Watanabe, Appl. Phys. Lett. 85, 449(2004))
Pr:Ti silicate (our work)
Hf silicate (Punchaipetch, J. Vac. Sci. Technol. A 22, 395 (2004)
Pr silicate (our work)
HfSiON
104
102
Jg (A/cm2)
wurde bei RT unter Ultra-Hochvakuum durch Elektronenstrahlverdampfen auf 2,5 nm dicke Pr-Silikat-Schichten
abgeschieden. Die Filme wurden in situ für 5 Minuten
im Temperaturbereich von 70 bis 880°C getempert.
Der Effekt der Ti-Zugabe wurde mittels Synchrotronstrahlungs-Photoelektronenspektroskopie untersucht.
Durch die Variation der Photonenanregungsenergie
konnte das Tiefenprofil zerstörungsfrei untersucht
werden. Diese Untersuchungen zeigen, dass durch
die Temperung eine Diffusion des Ti in das Pr-Silikat
aktiviert werden konnte. Es bildete sich eine homogene Schicht Pr:Ti-Silikat mit qualitativ hochwertigen
elektrischen Eigenschaften, wie in Abb. 27 durch die
Leckstromdichte Jg in Abhängigkeit von der äquivalenten Oxidschichtdicke (EOT) gezeigt wird. Basierend
auf den Ab-initio-Berechnungen wurde ein Verfahren
vorgeschlagen, wie Ti-Atome die elektrischen Eigenschaften der Grenzschicht verbessern können. Wie in
Abb. 28 dargestellt, werden durch die Oxydation von
Ti-Einschlüssen stress-getrappte Defekte eliminiert. Die
Pr:Ti-Silikat-Schicht weist größere k-Werte als Pr-SilikatSchichten auf, besitzt ein EOT von 1,2 nm und keine
Grenzschicht-Defektzustände.
Selected Projects
Mater ial s
100
10-2
SiO2
-4
10
10-6
10-8
1.0
1.5
2.0
2.5
3.0
EOT (nm)
Abb. 27: Leckstromdichte Jg von Pr-Silikaten und Pr:Ti-Silikaten
als Funktion der äquivalenten Oxidschichtdicke (EOT) im
Vergleich zu anderen veröffentlichten Werten von Hochk-Materialien.
Fig. 27: Leakage current density Jg as a function of equivalent
oxide thickness (EOT) for Pr silicate and Pr:Ti silicate in
comparison to values of other high-k materials published
in the literature.
tion on 2.5 nm thick Pr silicate layers. The fi lms were
annealed in situ for 5 minutes at temperatures ranging
from 70 to 880 °C. Synchrotron radiation excited photoelectron spectroscopy was applied to study the effect of Ti additives. Non-destructive depth profi ling by
varying the photon excitation energy shows that annealing activates the diffusion of deposited Ti into the
Pr silicate. A homogeneous Pr:Ti silicate layer is formed showing high quality electrical properties in leakage
current density Jg versus equivalent oxide thickness
(EOT) (Fig. 27). On the basis of ab initio calculations,
a mechanism has been proposed whereby Ti atoms
could improve the electrical interface properties. As
shown in Fig. 28, through the oxidation of Ti inclusions,
stress-trapped defects burn away. The Pr:Ti silicate layer shows higher k values in comparison to Pr silicate,
no interface defect states, and an EOT of 1.2 nm.
Abb. 28: Durch Oxidation der Ti-Einschlüsse werden die durch Stress
erzeugten Trap-Defekte verdrängt:
- O wird von der defekten Grenzschicht in die Ti-Einschlüsse gezogen,
- Si wird durch Ti aus dem Silikat verdrängt,
- Si wächst wieder an der Grenzfläche.
(große Kugeln: Silizium, kleine Kugeln: Sauerstoff)
Fig. 28:
Through the oxidation of Ti inclusions, stress-trapped
defects burn away:
- O is drawn into Ti inclusions from defected interface,
- Si is expelled from silicate by Ti ejected from inclusions,
- Si is re-grown at the interface.
(large bullets: silicon, small bullets: oxygen)
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
51
Ausgewählte Projekte
Mater ialien
Selected Projects
Mater ial s
MIM Kondensatoren mit verbesserten elektrischen Parametern
MIM Capacitors with Improved Electrical Parameters
Metall-Isolator-Metall (MIM) -Kondensatoren finden großes Interesse als passive Bauelemente in siliziumbasierten Schaltkreisen für Hochfrequenz- und Mischsignalanwendungen. Der Ersatz von konventionellem SiO2
und Si3 N 4 durch Materialien hoher Dielektrizitätskonstante ist substantiell für die Reduzierung der Kondensatorfläche. Unterschiedliche Hoch-k-Materialien wie
Al2O3, AlTiO x, AlTaO x, (HfO2)1-x (Al2O3 ) x, HfO2, ZrO2, Y2O3,
Ta 2O5 und Pr2O3 wurden als Kandidaten für MIM-Kondensatoren untersucht.
Metal-insulator-metal (MIM) capacitors as passive devices in silicon radio-frequency and mixed-signal integrated circuit applications attract considerable attention. The replacement of conventional SiO2 and Si3 N 4
by high-k dielectric materials is substantial to reduce
the capacitor’s area. Recently, several high-k materials such as Al2O3, AlTiO x, AlTaO x, (HfO2)1-x (Al2O3 ) x, HfO2,
ZrO2, Y2O3, Ta2O5 and Pr2O3 have been investigated as
candidates for MIM capacitors.
20
k = 15
k = 15
ΦB = 0.9 eV
PrTiO3
16
Leakage parameter (fA/pF*V)
Capacitance Density (fF/µm2)
18
5 fF/µm2
1000
Pr2O3
14
Ta2O5
12
HfO2
10
8
6
ITRS 2004
4
2
100
ITRS 2004
10
1
PrTiO3
PrTiO
3
Pr2O3
Pr 2O3
0.1
0
0
10
20
30
40
50
60
70
0
10
Physical Thickness (nm)
Abb. 29: Kapazitätsdichte als Funktion der physikalischen Schichtdicke für verschiedene Hoch-k-Materialien, eingeschlossen
Pr2O3 und PrTixO y . Das Ziel der ITRS ist hier und in den
folgenden beiden Abbildungen ebenfalls eingezeichnet.
Fig. 29: Capacitance density as a function of physical thickness
for different high-k dielectrics including Pr2O3 and PrTiO3 .
The goal of the ITRS is also marked here and in the
following two figures.
Wir berichten erstmalig über die Realisierung von auf
einer TiN x-Metallelektrode abgeschiedenen Kondensatoren mit amorphem dielektrischem PrTi xO y und einer
Al-Top-Elektrode. Die PrTi xO y -Kondensatoren wurden
im thermischen Budget der Back-End-Prozesse gefertigt. Die hygroskopische Natur der Lanthanid-Oxide
wie Pr2O3 ist ein bekanntes Phänomen. Durch Wasserabsorbtion in Pr2O3 bilden sich negative Festladungen.
Die Beimengung von TiO2 zu Pr2O3 kann die Wasseraufnahme aus der Luft unterdrücken.
52
k = 15
ΦB B= 1.0 eV
20
30
40
50
60
Film Thickness (nm)
Abb. 30: Leckstromparameter in Abhängigkeit von der Schichtdicke.
Fig. 30: Leakage parameter as a function of film thickness.
We are reporting for the fi rst time on the capacitor performance of amorphous PrTi xO y dielectric fi lms which
were deposited on TiN x metal electrodes to form MIM
structures with Al top electrodes. The PrTi xO y capacitors were fabricated within the temperature budget of
the back end of line process. The hygroscopic nature
is a well-known characteristic of lanthanide oxides as
Pr2O3. Negative fi xed charges can be formed by water
absorption of Pr2O3 layers. The addition of TiO2 into
the Pr2O3 matrix can suppress the water absorption
from air.
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Mater ialien
Die Kapazitätsdichten bei 100 kHz für verschiedene
PrTi xO y -Schichtdicken sind in Abb. 29 dargestellt. Zum
Vergleich sind Messpunkte anderer Hoch-k-Materialien beigefügt. Zur Bestimmung der dielektrischen
Konstante wurde ein Einschicht-Kondensator-Modell,
repräsentiert durch die schwarze Kurve, an die Messpunkte angepasst. Der erhaltene k-Wert für amorphe
PrTi xO y -Schichten beträgt 15. Der bei 1 V bestimmte
Strom-Parameter in Abhängigkeit von der Schichtdicke
des PrTi xO y und Pr2O3 ist in Abb. 30 dargestellt.
Abb. 31 zeigt den quadratischen Kapazitäts-Spannungskoeffizienten (VCC) der PrTi xO y -MIM-Kondensatoren als Funktion der Kapazitätsdichte. Zudem sind
Voltage Linearity at 10 kHz
Quadratic VCC (ppm/V2)
10000
1000
Selected Projects
Mater ial s
The capacitance densities at 100 kHz for various PrTixOy
layer thickness are shown in Fig. 29. Measurement
points of other high-k materials are also depicted for
the sake of comparison. A single layer capacitor model represented by the solid line was used to determine the dielectric constant. The received k value of
amorphous PrTi xO y films is about 15. The leakage parameter determined at 1 V versus both PrTi xO y and Pr2O3
layer thickness are shown in Fig. 30.
Fig. 31 illustrates the quadratic voltage coefficients of
the capacitance (VCC) of PrTi xO y MIM capacitors as a
function of the capacitance density. Moreover, results
of other material candidates are presented. The VCCs,
caused by bulk-dielectric traps near the dielectric/metal interface, are strongly dependent on frequency.
The MIM capacitor with a PrTi xO y layer thickness of
20 nm shows a capacitance density of 5 fF/µm2 and a
quadratic voltage coefficient of 1000 ppm/ V2, which
means that it can meet the requirements of the ITRS
(International Technology Roadmap for Semiconductors) 2004.
PrTiO3
HfO2
100
Ta2O5
HfO2 + SiO2
10
ITRS 2004
1
0
5
10
15
Capacitance Density (fF/µm2)
Abb. 31: Quadratischer Spannungskoeffizient der Kapazität (VCC)
als Funktion der Kapazitätsdichte für verschiedene Hochk-Materialien einschließlich PrTiO3.
Fig. 31: Quadratic voltage coefficients of capacitance (VCC) as
a function of capacitance density for different high-k
dielectrics including PrTiO3.
Messungen anderer Kandidaten dargestellt. Aufgrund
von dielektrischen Traps nahe der Dielektrikum/MetallGrenzschicht sind die VCCs stark frequenzabhängig.
Der MIM-Kondensator mit einer PrTi xO y -Schichtdicke
von 20 nm zeigt eine Kapazitätsdichte von 5 fF/µm2
und einen quadratischen Spannungskoeffizienten von
1000 ppm/ V2 und kann somit Anforderungen der ITRS
(International Technology Roadmap for Semiconductors) 2004 erfüllen.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
53
Ausgewählte Projekte
Mater ialien
Selected Projects
Mater ial s
Heteroepitaktische Si/Pr2O3/SiStrukturen
Heteroepitaxial Si/Pr2O3/Si
Structures
Bei der rasanten Skalierung in der Mikroelektronik
sind heteroepitaktische Materialsysteme von besonders großem Interesse, da gitterangepasste Systeme
Funktionalität mit hoher struktureller Stabilität kombinieren. Heteroepitaktische Si/Pr2O3/Si-Strukturen
sind vielversprechende Halbleiter-Isolator-Halbleiter
(SIS) Stapel für zukünftige Anwendungen als Siliconon-Insulator (SOI) -Wafer oder für innovative Transistordesigns wie Multiple-Gate-Transistoren.
In the course of aggressive scaling in microelectronics, heteroepitaxial materials systems are of special
interest because lattice matched systems combine
functionality with high structural stability. Heteroepitaxial Si/Pr2O3/Si structures are promising semiconductor-insulator-semiconductor (SIS) stacks for future
applications as engineered wafer materials such as
silicon-on-insulator (SOI) or for innovative transistor
designs, e.g. multiple gate transistors.
Hier wird das Wachstum solcher Strukturen auf Si(111)
mittels Molekularstrahlepitaxie (MBE) beschrieben.
Das Wachstumsverhalten von Pr2O3 -Schichten auf
Si(111) wurde mittels Reflektion hochenergetischer
Elektronen (RHEED) untersucht. Mittels Raster-TunnelMikroskopie (STM) wurde die Bildung einer geschlossenen Oxidschicht visualisiert. Analysen durch Syn-
Here, we are reporting on the molecular beam epitaxy (MBE) growth of such structures on Si(111) wafers. The growth behaviour of Pr2O3 films on Si(111)
was studied by reflection high energy electron diffraction (RHEED) to determine the growth mode. Scanning
tunnelling microscopy (STM) was applied to visualize
the formation of a closed oxide overlayer. Synchro-
Abb. 32: TEM-Untersuchung des heteroepitaktischen Si/Pr2O3/
Si(001)-Systems: (a) Übersichtsaufnahme des Querschnittes, (b) und (c) sind hochaufgelöste TEM-Abbildungen
entlang der Si-Bulk [2 ]-Richtung der Grenzflächen
Si(111)/Pr2O3 und Pr2O3 /Si(111) Epischicht.
Fig. 32:
chrotron Radiation-Grazing-Incidence X-ray Diffraction
(SR-GIXRD) zeigen den Übergang von pseudomorphem
zu volumenartigem Verhalten im ultradünnen Schichtdickenbereich < 10 nm. Dickere Oxidschichten (bis zu
50 nm) wurden mittels XRD und Röntgenreflektometrie
(XRR) untersucht, um die kristalline Qualität und die
Oberflächenrauhigkeit zu bestimmen. Es wurde festgestellt, dass Pr2O3 -Schichten in der hexagonal orientierten (0001) -Phase auf Si(111) wachsen. Durch eine
Temperung kann aber das Oxid in die kubische Pha-
tron radiation-grazing incidence X-ray diffraction (SRGIXRD) studies monitored the transition from pseudomorphism to bulk behaviour in the ultra-thin thickness
regime < 10 nm. Thicker oxide layers (up to 50 nm)
were studied by XRD and X-ray reflectivity (XRR) to monitor the crystalline quality and surface roughness. It
was discovered that the Pr2O3 film grows in the (0001)
oriented hexagonal phase on Si(111) but an annealing
procedure can transform the oxide in its cubic phase
with (111) orientation. The Si overgrowth was carried
54
TEM study of the heteroepitaxial Si/Pr 2O3 /Si(001)
system: (a) Overview cross section image, (b) and (c)
show highly resolved cross section TEM images along
the Si bulk [2 ] direction of the Si(111) substrate/
Pr 2O3 and Pr 2O3 /Si(111) epilayer interface.
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se mit (111) -Orientierung umgewandelt werden. Das
Überwachsen mit Si wurde sowohl auf hexagonalen als
auch auf kubischen Oxidfilmen durchgeführt, um den
Grad der Verspannung der Si-Epischicht anzupassen.
Zur Bestätigung der durch Röntgen-Diffraktrometrie
erhaltenen Ergebnisse wurden TEM-Aufnahmen gemacht. Die Ergebnisse sind in Abb. 32 zusammengefasst. Abb. 32(a) zeigt eine Querrschnittsaufnahme
der Si/Pr2O3/Si(111) -Heterostruktur. Die aus XRR-Messungen erhaltenen Schichtdicken zeigen eine Struktur,
die aus einer 52 nm dicken Pr2O3 -Schicht und einer
17 nm dicken Si-Schutzschicht besteht. Man kann deutlich erkennen, dass die Pr2O3/Si(111) -Substrat-Grenzschicht sehr glatt, die Grenze zwischen der Pr2O3 Schicht und der Si-Epischicht jedoch viel rauher ist.
Abb. 32(b) und 32(c) sind hochaufgelöste Gitterabbildungen der Pr2O3/Si(111) - und der Si-Epischicht/Pr2O3 Grenzschichten. Die Blickrichtung ist entlang der <11
>Si(111) in-plane Richtung, was man aus der Tatsache
schließen kann, dass die Si(111) -Gitterebenen vertikal geschichtet sind. Die angrenzenden hexagonalen
(0001) Pr2O3 -Ebenen besitzen ebenfalls eine On-topStapelung in dieser Blickrichtung. Neben den bereits
diskutierten Unterschieden der Grenzschicht-Rauhigkeiten zeigt sich, dass die beiden Pr2O3/Si-Grenzschichten typischerweise keine Grenzschicht-Reaktionen aufweisen.
Selected Projects
Mater ial s
out on hexagonal as well as cubic oxide layers to tailor
the degree of strain in the Si epilayer.
TEM measurements were performed to corroborate the
results of the X-ray diffraction studies and are summarized in Fig. 32. Fig. 32(a) shows a cross section overview image of the Si/Pr2O3/Si(111) heterostructure.
Film thickness values derived from XRR fits suggested a structure composed of a 52 nm thick Pr2O3 film
and a 17 nm thick Si capping layer. One can clearly
see that the Pr2O3/Si(111) substrate interface is very
smooth and the boundary between the Pr2O3 film and
the Si epilayer is much rougher. Figs. 32(b) and 32(c)
are highly resolved direct lattice images of the Pr2O3/
Si(111) substrate and the Si epilayer/Pr2O3 interfaces.
The view direction is along a <11 >Si(111) in-plane direction, as can be inferred from the fact that the Si(111)
lattice planes appear vertically stacked. It is noted that
adjacent (0001) hex-Pr2O3 planes also exhibit such ontop stacking from this line of vision. Besides the differences of the interface roughnesses already discussed, a common feature of the two Pr2O3/Si interfaces
is that no sign of an interfacial reaction can be observed.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
55
Ausgewählte Projekte
Mater ialien
Selected Projects
Mater ial s
Si-basierte Lichtemitter
Si-based Light Emitters
Dieser Beitrag befasst sich mit den Grundlagen für
CMOS-kompatible Lichtemitter. Ziel ist die Optimierung eines Emitters, der bei Ď ~ 1,5 µm arbeitet und
für 300 K eine Quanten-Effizienz von einigen Prozent
aufweist.
This contribution addresses the basis of CMOS compatible light-emitting devices. The goal is to optimize
an emitter for Ď ~ 1.5 µm, which has a quantum efficiency of a few percent at 300 K.
Die Motivation für diese Arbeiten ergibt sich aus
den Grenzen des Metall-Leitbahnsystems hinsichtlich
Geschwindigkeit, Verlustwärme, Signal-Übersprechen
usw., weshalb bereits in einigen Jahren eine zusätzliche optische Signal-Übertragung auf dem Chip zwingend notwendig sein wird.
Zur „Bandkanten-Lumineszenz bei 1,1 µm an implantierten Strukturen“ haben wir, neben der bereits in der
Literatur beschriebenen B-Implantation in n-Si, auch
0.8
Internal Efficiency (%)
BB
0.7
300K
0.6
D4
0.5
80K
0.4
0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25
0.3
0.2
0.1
0.0
Phosphorous implant
50
100
150
200
250
300
Temperature (K)
Abb. 33: Anomalie im Temperaturverhalten der Elektrolumineszenz
in einer in Durchlassrichtung gepolten LED, hergestellt
durch Phosphor-Implantation in p-Silizium. Der Einsatz
im Bild zeigt das Lumineszenzspektrum: Bei 300 K
dominiert die Bandkantenlumineszenz (BB).
Fig. 33: Anomalous T-behaviour of electroluminescence in a
forward biased LED made by P-implant in p-type Si. The
inset shows the luminescence spectrum: at 300 K the
band-edge luminescence (BB) dominates.
die P-Implantation in p-Si untersucht. Abb. 33 zeigt
dafür die anormale Zunahme der Intensität der Elektro-Lumineszenz mit der Temperatur. Bisher haben wir
für P-Implant eine interne Effizienz von 2% bei 300 K
nachgewiesen. Unser Modell, das die eigenen Messdaten sowie Daten aus der Literatur beschreiben kann,
lässt eine Verbesserung der Effizienz auf mindestens
5% erwarten. Es führt die effiziente Lichtemission auf
56
This work has been motivated by the limitations of the
metal interconnect system in terms of speed, heat penalty, cross talk etc. According to these limitations,
on-chip optical interconnects will become necessary
within a few years.
With respect to “Band-edge luminescence at 1.1 µm
from implanted Si devices”, we analyzed, in addition to
the B implantation in n-type Si already described in the
literature, P implantation in p-type Si. Fig. 33 shows
the anomalous temperature behaviour of the electroluminescence. The best value for the internal quantum
efficiency at 300 K we have been able to reach so far
is 2% for P implantation. We developed a model that
allows us to describe the data measured on our own
samples and experimental data given in the literature.
As it stands, we can see the potential for increasing
the efficiency to at least 5%. According to this model,
the efficient light emission is a consequence of the
perfection of the Si material in the vicinity of the implanted region rather than the reduction of non-radiative channels due to the strain fields of implantationinduced dislocation loops, as suggested in the literature. Furthermore, our model explains the anomalous
temperature behaviour of the luminescence.
An alternative for Si-based light emission is the application of “D1-band dislocation luminescence at 1.5 µm”.
As shown in Fig. 34, we found that the D1 emission
dominates in structures consisting of a regular dislocation network (formed by wafer bonding at MPI Halle), exhibiting an intensity which is at least 10 times
higher than the intensity of the band-edge line. Accordingly, we expect that the quantum efficiency of LED
structures, which have been optimized with respect
to the D1 emission, might considerably exceed that of
implanted structures.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
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Mater ialien
D1
15000
80 K
60
Intensity (a.u.)
50
PL Intensity (a.u.)
Selected Projects
Mater ial s
10000
BB
80k
40
30
D3
20
D4
D1
D2
10
0
140 K
0.7
0.8
0.9
1.0
1.1
1.2
Energy (eV)
5000
290 K
(BB)
0
0.8
Photon Energy (eV)
eine hohe Perfektion des Si in der Nachbarschaft des
implantierten Gebietes zurück und nicht, wie in der
Literatur angegeben, auf eine Reduzierung von nichtstrahlenden Rekombinations-Pfaden durch das Verzerrungsfeld an den implantationsinduzierten Versetzungsschleifen. Weiterhin kann es auch das anormale
Temperaturverhalten erklären.
Eine andere Möglichkeit für die Si-basierte Lichtemission besteht in der Nutzung der „D1-Band VersetzungsLumineszenz bei 1,5 µm“. Wie Abb. 34 demonstriert,
konnten wir nachweisen, dass in Strukturen mit einem
regulären Versetzungsnetzwerk (erzeugt durch Waferbonden am MPI Halle) die D1-Emission dominiert und
mehr als zehnmal intensiver ist als die Bandkantenlinie.
Dies lässt erwarten, dass die Quanten-Effizienz in LEDStrukturen, die auf D1-Emission optimiert sind, die von
implantierten Strukturen deutlich übersteigen sollte.
1.0
Abb. 34: Photolumineszenz-Spektrum einer Si-Struktur mit einem
durch Waferbonden hergestellten Versetzungsnetzwerk
200 nm parallel zur Oberfläche. Die D1-Emission dominiert im analysierten Bereich von 80-290 K. Im kleinen
Bild ist zum Vergleich ein typisches Spektrum von
Silizium mit Versetzungen.
Fig. 34: Photoluminescence spectrum of a Si structure with a dislocation network 200 nm parallel to the surface, formed
by wafer bonding. The D1 emission dominates in the
analyzed range of 80-290 K. See the inset showing a
typical spectrum of dislocated Si for comparison.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
57
Gemeinsames Labor IHP/BTU
IHP/BTU Joint Lab
Gemeinsames Labor
IHP/BTU
IHP/BTU Joint Lab
Das Gemeinsame Labor IHP/BTU auf dem Campus der
Brandenburgischen Technischen Universität in Cottbus
wurde im Jahre 2000 mit dem Hauptziel gegründet, die
Forschungspotentiale beider Partner zu bündeln und
leistungsfähige überkritische Potentiale für anspruchsvolle interdisziplinäre Forschungen zu schaffen.
The IHP/BTU Joint Lab, located on the campus of the
Technical University of Brandenburg Cottbus, was
founded in 2000. The main objective was to bundle
the research resources of both partners and to establish capable supercritical potentials for ambitious interdisciplinary research.
An den Arbeiten, die auf moderne Halbleitermaterialien, Halbleitertechnologien und den Schaltungs- und
Systementwurf ausgerichtet sind, beteiligen sich seitens der BTU vor allem die Lehrstühle
The research work ranges from modern semiconductor materials and technologies to the design of circuits
and systems. The following chairs of the BTU Cottbus
are involved:
-
Experimentalphysik/Materialwissenschaften
-
Experimental Physics/Materials Science
-
Theoretische Physik
-
Theoretical Physics
-
Physikalische Chemie
-
Physical Chemistry
-
Systeme
-
Systems
-
Mikroelektronik
-
Microelectronics
Bund und Land Brandenburg fördern im Rahmen des
Hochschul- und Wissenschaftsprogramms im Gemeinsamen Labor den Aufbau eines Kompetenzzentrums
für Halbleitermaterialien und -technologien.
The federal government and the State of Brandenburg
support the development of a center of competency
for semiconductor materials and technologies at the
Joint Lab within the framework of their University and
Science Program.
Ausgehend von einer Analyse der künftigen Entwicklung
der Halbleiterelektronik und der Ausrichtung des IHP
wurden in 2004 folgende Arbeitsrichtungen als langfristige Forschungsschwerpunkte herausgearbeitet:
Based on an analysis of future trends in the development of semiconductor electronics and IHP’s research
focus, the following topics were identified in 2004 as
prospective long-term research directions:
-
Advanced Silicon (Silicium für zukünftige Halbleitertechnologien und -schaltungen)
-
Advanced Silicon (silicon for future technologies
and circuits)
-
Hoch-k-Materialien (neue Dielektrika für die Nanoelektronik)
-
High-k materials (new dielectrics for nanoelectronics)
-
Kopplung Halbleiteroberfläche – biologische Medien
-
Linkage between semiconductor surface and biomedia
-
Optische Datenübertragung auf dem Chip
-
On-chip optical data transmission
-
Quantenbauelemente
-
Quantum devices
-
Diagnostik für Material- und Technologieentwicklung des IHP.
-
Diagnostics support for IHP materials and technologies.
Die Forschungsarbeiten sind überwiegend grundlagenorientiert und haben ausgeprägten Vorlaufcharakter.
Durch die enge Kopplung mit dem IHP besteht dabei
die einzigartige Chance, neue Erkenntnisse bis zu anwendungsreifen Lösungen zu führen. Als aussichtsreich sind besonders die Arbeiten zu Si-basierten Lichtemittern und Quantenbauelementen hervorzuheben.
The research conducted is predominantly fundamental and has a distinct search character. The close link
to IHP’s capabilities provides a unique opportunity to
generate implementable solutions from new scientific
insights. Si-based light emitters and quantum devices
are among promising research topics.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
59
Gemeinsames Labor
IHP/BTU
IHP/BTU Joint Lab
Allein zu Halbleitermaterialien und -technologien sind
im laufenden Jahr 16 Publikationen entstanden, 33 Vorträge – darunter 9 eingeladene – gehalten und 2 Patente angemeldet worden.
Research carried out this year on semiconductor materials and technology alone has resulted in 16 publications, 33 presentations – 9 invited –, and 2 filed
patents.
Für die laufenden Forschungsprojekte wurden in 2004
insgesamt über 500 000 Euro Drittmittel eingeworben.
A total third party funding of more than Euro 500,000
was raised for the running projects.
Neues Elektronensondensystem mit Kathodolumineszenzausrüstung
erweitert diagnostisches Potential.
New electron probe system with cathodoluminescence attachments
enhances diagnostic capabilities.
Prof. Dr. Eicke R. Weber, University of California, Berkeley (zweiter
von links) beim Besuch des Gemeinsamen Labors im November 2004.
Prof. Eicke R. Weber, University of California, Berkeley (second from
left) visiting the Joint Lab in November 2004.
Eine wichtige Aufgabe stellt der Ausbau der internationalen Vernetzung und die Gewinnung ausländischer Experten für die Mitarbeit dar. Ausdruck des
erfolgreichen Wirkens des Gemeinsamen Labors auf
diesem Gebiet sind seine internationale Zusammensetzung, die Beteiligung an einem japanischem Standardisierungsprojekt für Si-Wafer (siehe N. Inoue et
al., Proc. of JSPS, 2004, pp. 123-128), und die langjährige aktive Mitwirkung in internationalen Konferenzkomitees (z.B. Conference und Program Co-Chair bei
11. Internationaler GADEST-Konferenz 2005).
The extension of the international integration and recruitment of foreign experts for collaboration is an
important task for the capabilities of the Joint Lab.
The international composition of the Joint Lab staff,
the participation in a Japanese standardization project
for silicon wafers (see N. Inoue et al., Proc. of JSPS,
2004, pp. 123-128) and longtime active involvement in
international conference committees (e.g. Conference
and Program Co-Chair of 11th GADEST Conference in
2005) emphasize the successful work of the Joint Lab
in this area.
Das Gemeinsame Labor unterstützt und erweitert das
Lehrangebot der BTU in den Studiengängen Physik,
Physik der Halbleitertechnologie, Informatik und Elektrotechnik mit Vorlesungen, Übungen und Praktika. In
2004 wurden 3 Doktoranden und 5 Diplomanden betreut.
The Joint Lab supports and broadens the educational offers of the BTU with courses in Physics, Physics
of Semiconductor Technology, Computer Science and
Electrical Engineering through lectures, tutorials and
lab practicals. In 2004 5 graduates and 3 PhD students were supervised by Joint Lab staff.
Weiterführende Informationen über das Gemeinsame
Labor sind unter www.tu-cottbus.de/jointlab abrufbar.
For more information about the Joint Lab please visit
the website www.tu-cottbus.de/jointlab.
60
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Gemeinsames Labor
IHP/BTU
IHP/BTU Joint Lab
Die Mitarbeiter des Gemeinsamen Labors mit dem Präsidenten der BTU Cottbus, Prof. Dr. Ernst Sigmund (links außen) und dem Direktor des
Gemeinsamen Labors, Prof. Dr. Hans Richter (zweiter von rechts).
The employees of the Joint Lab with the President of BTU Cottbus, Prof. Ernst Sigmund (far left) and the Director of Joint Lab, Prof. Hans
Richter (second from right).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
61
Konferenzen und Workshops
Conferences and Workshops
Konferenzen
und Workshops
Conferences
and Workshops
Das IHP beteiligte sich aktiv an der Organisation internationaler Konferenzen und Tagungen. Die Themen der
Veranstaltungen reichten von Materialien bis zur Systementwicklung und spiegelten so die Forschungsgebiete des IHP wider.
Im Folgenden ist eine Auswahl der 2004 mit aktiver
Beteiligung des IHP organisierten Konferenzen und Tagungen beschrieben.
The IHP was active in organizing international conferences and workshops. The topics spanned from system design to materials, reflecting the research areas
of the IHP.
A selection of the international conferences and workshops, organized in 2004 with active contributions of
the IHP, are described below.
2. Internationale Konferenz für Wired/Wireless
Internet Communications WWIC 2004, 04.-06.
Februar 2004, Frankfurt (Oder).
2nd International Conference on Wired/Wireless
Internet Communications WWIC 2004, February
04-06, Frankfurt (Oder).
Der Fokus der WWIC sind heterogene Netzwerkarchitekturen. Die Integration mobiler Endgeräte ins
Internet führt zu einer Reihe neuer Herausforderungen, wie Design und Evaluierung von Protokollen, dynamische Integration, Performanz-Betrachtungen sowie
neue Performanz-Metriken und Schichten übergreifende Interaktionen. Die Anzahl sowie die Qualität der Einreichungen zeigt, dass die WWIC auf einem guten Weg
ist sich als eine der bedeutenden Konferenzen in diesem Gebiet zu etablieren.
Der Tagungsband wurde in der angesehenen Reihe
„Lecture Nodes in Computer Science“ des Springer
Verlages veröffentlicht. Die Konferenz wurde vom IHP
organisiert und im Institut durchgeführt.
WWIC is dedicated to bridging the gap between wired
and wireless Internet. The issue of integrating mobile
devices in the Internet poses many challenges such as
the design and evaluation of protocols, the dynamics
of the integration, the performance tradeoffs, the need
for new performance metrics, and the cross-layer interactions. The number and the quality of submissions
indicates that WWIC is well on the way to establishing
itself as one of the major events in this field.
The proceedings have been published in the prestigious "Lecture Nodes in Computer Science" Series of
Springer. The conference was organized by IHP staff
and held at the institute.
Peter Langendörfer (IHP) war einer der Vorsitzenden
des Programmkomitees. Daniel Dietterle, Jan Schäffner und Heike Wasgien (alle IHP) arbeiteten im Organisationskomitee.
Peter Langendörfer (IHP) was one of the Technical Program Chairs, and Daniel Dietterle, Jan Schäffner and
Heike Wasgien (all IHP) were part of the organizing
committee.
2. Internationales SiGe Technology and Device
Meeting ISTDM 2004, 16.-19. Mai 2004, Frankfurt (Oder).
2nd International SiGe Technology and Device
Meeting, May 16-19, 2004, Frankfurt (Oder).
116 Experten diskutierten aktuelle Ergebnisse der
SiGe-Forschung auf den Gebieten Materialwissenschaften, Prozesstechnologie, Bauelementeentwicklung und
Schaltkreisdesign. Die Kombination aus Grundlagenund angewandter Forschung wird deutlich in der Zusammensetzung der Teilnehmer (44% von Universitäten, 34% von Forschungsinstituten und 22% aus der
Industrie). Die Kongressteilnehmer kamen aus 14 europäischen und asiatischen Ländern sowie den USA.
Der Tagungsband wurde im Februar 2005 in „Materials Science in Semiconductor Processing” (Elsevier)
veröffentlicht.
Altogether 116 experts met to discuss the current status of SiGe materials science, process technology, devices, and circuit design. This combination of basic
and applied research was reflected in the composition
of the participants (44% from universities, 34% from
state-run research institutes, and 22% from industry).
The participants came from 14 European and Asian
countries and from the USA.
The proceedings of the conference are published as
the February 2005 issue of “Materials Science in Semiconductor Processing” (Elsevier).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
63
Konferenzen
und Workshops
Conferences
and Workshops
Die ISTDM wurde vom IHP organisiert und im Kongresscentrum „Kleist Forum“ in Frankfurt (Oder) durchgeführt.
Bernd Tillack (IHP) führte den Vorsitz des Programmkomitees. Gerhard Fischer, Monika Schultze und Yuji
Yamamoto (alle IHP) waren Mitglieder des Organisationskomitees.
The conference was organized by the IHP and held at
the Congresscenter "Kleist Forum" in Frankfurt (Oder).
Bernd Tillack (IHP) was Chairman of the Program Committee. Gerhard Fischer, Monika Schultze, and Yuji Yamamoto (all IHP) were members of the organizing committee.
Das Organisationskomitee der ISTDM 2004./Organization Committee of the ISTDM 2004.
Prof. Junichi Murota (Tohoku University Sendai), Dr. Bernd Tillack (IHP) und Prof. Erich Kasper (University of Stuttgart) [von links nach
rechts/from left to right].
Symposium C des Frühjahrstreffens der E-MRS:
Neue Materialien in der zukünftigen Siliziumtechnologie, 24.-28. Mai 2004, Strassburg (Frankreich).
Symposium C of the E-MRS 2004 Spring Meeting:
New Materials in Future Silicon Technology, May
24-28, 2004, Strasbourg (France).
Das Symposium konzentrierte sich auf zukünftige Herausforderungen für die Materialforschung durch die
weitere Strukturverkleinerung silizium-basierter Bauelemente, die in den nächsten Jahren die physikalischen Grenzen erreichen werden. Die Veranstaltung
war insbesondere der Charakterisierung und der Auswahl neuer Materialien für die Integration in CMOSTechnologien gewidmet, bestimmt von den praktischen
Anforderungen der Industrie.
The symposium focused on the future challenges in
material science to the continued scaling of siliconbased devices reaching the physical limits of miniaturization within the next few years. It was devoted to
the characterization and selection of new materials for
the integration into CMOS technology in response to
practical demands ensuing from the industry.
Hans-Joachim Müssig and Jarek Dabrowski (IHP) were
members of the symposium organizers.
Hans-Joachim Müssig und Jarek Dabrowski (IHP) waren
Mitglieder des Organisationskomitees.
8. BMBF Statusseminar Mobile Kommunikation,
(Bundesministerium für Bildung und Forschung),
13.-15. Juli 2004, IHP Frankfurt (Oder).
8th BMBF Status Seminar Mobile Communications
(Federal Ministry for Education and Research),
July 13-15, 2004, IHP Frankfurt (Oder).
Im Rahmen des 8. Statusseminars des BMBF Förderbereichs Mobile Kommunikation stellten über 100 eingeladene Wissenschaftler aus Industrie und Forschung
More than one hundred scientists from industries and
academia presented their latest findings during the
8 th BMBF Status Seminar in Frankfurt (Oder). Besides
64
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Konferenzen
und Workshops
ihre jüngsten Forschungsergebnisse in Fachvorträgen
am IHP in Frankfurt (Oder) vor. Darüber hinaus wurden
zahlreiche Poster und funktionsfähige Demonstratoren
vorgestellt.
Das Statusseminar wurde so zu einem Forum des regen Meinungsaustausches führender Wissenschaftler
auf dem Gebiet der mobilen Kommunikation. Als Gastgeber hat das IHP diese Gelegenheit genutzt, die eigenen Forschungsvorhaben einem breiten und sachkundigen Publikum vorzustellen.
Conferences
and Workshops
technical presentations, a poster presentation and an
exhibition of working demonstrators were organized.
Thus the Status Seminar became a forum for intense discussions between experts in the field of mobile communications. As the host of this event, the
IHP used this opportunity to present its own research
projects and findings to a broad and competent community.
The local organizer of this event was Rolf Kraemer
(IHP).
Der lokale Organisator des Seminars war Rolf Kraemer (IHP).
9. Augustusburg Conference of Advanced Science:
Das Silizium-Zeitalter, 23.-25. September 2004,
Augustusburg.
9th Augustusburg Conference of Advanced Science:
The Silicon Age, September 23-25, 2004, Augustusburg.
Diese Veranstaltung war vorgesehen als Forum für die
Bewertung und Diskussion verschiedener Aspekte des
Siliziumszeitalters. Vortragende aus Hochschulen und
der Industrie präsentierten ihren Blick auf die Anwendung des Siliziums in der Mikroelektronik, Photovoltaik und Photonik.
This event provided a forum for reviewing and discussing different aspects of the silicon age.Speakers
from academia and industry represented their views
on silicon used for microelectronics, photovoltaics
and photonics.
Martin Kittler (IHP) war der Vorsitzende dieser Konferenz und Hans Richter (IHP) Mitglied im Organisationskomitee.
Martin Kittler (IHP) was the Chairman of this conference and Hans Richter (IHP) was member of the organizing committee.
IHP Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, 30. September 2004, Frankfurt (Oder).
IHP Workshop High-Performance SiGe:C BiCMOS
for Wireless and Broadband Communication, September 30, 2004, Frankfurt (Oder).
Vertreter von 27 Firmen und wissenschaftlichen Einrichtungen aus acht Ländern nutzten das Treffen, um
sowohl bereits verfügbare Technologien als auch neueste Forschungsarbeiten des IHP kennen zu lernen.
Neben aktiven Nutzern der IHP-Technologien trafen
sich auf dem Workshop auch zahlreiche neue Interessenten für eine Kooperation mit dem Institut. Die Veranstaltung bot nicht nur neueste Informationen aus
erster Hand, sondern auch Gelegenheit für zahlreiche
persönliche Gespräche und neue Kontakte.
Participants from 27 companies and research institutions from eight countries used the meeting to learn
about the available technologies as well as the latest
research at the IHP.
In addition to active users of IHP’s technologies, numerous potential collaborators with the IHP also met
at this workshop. The event offered not only the latest
first-hand information, but also the opportunity to engage in many personal discussions and to forge new
contacts.
Der Workshop wurde durch Wolfgang Kissinger (IHP)
organisiert.
The workshop was organized by Wolfgang Kissinger
(IHP).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
65
Zusammenarbeit und Partner
Collaborators and Partners
Zusammenarbeit
und Par tner
Collaborators
and Par tners
Industrie/Industry
A*Star, Singapore
Micronas GmbH, Germany
ABS GmbH, Germany
Mitsubishi Electric Information Technology Centre
Europe B.V., France
ACCESS e.V., Germany
Acquiris, Switzerland
Motorola S.A.S., France
AdMOS GmbH, Germany
Nokia GmbH, Germany
advICo microelectronics GmbH, Germany
Nokia Research Centre, Germany
Agilent Technologies GmbH, Germany
Philips CFT, Eindhoven, The Netherlands
AIXTRON AG, Germany
Philips Electronics Netherland B.V., The Netherlands
Alcatel SEL AG, Germany
Philips Electronics Ltd., UK
alpha microelectronics GmbH, Germany
Philips Research Laboratories Aachen, Germany
AMD Inc., Germany
Philips Semiconductor GmbH, Germany
ARMINES, France
PropheSi Technologies, USA
Ascom Systec AG, Switzerland
Robert Bosch GmbH, Germany
ASM Inc., USA
RWE Schott Solar GmbH, Germany
Atmel Germany GmbH, Germany
Samsung Electronics Co. Ltd., Republic of Korea
Centellax Inc., Santa Rosa, USA
Sennheiser electronic GmbH & Co. KG, Germany
centrotherm GmbH & Co. KG, Germany
Siemens AG, Germany
CML Microsystems Plc, UK
Siemens Austria AG, Austria
CNR IMM, Catania, Italy
SiGe Semiconductor Inc., Canada
CoreOptics GmbH, Germany
Signalion GmbH, Germany
CSEM SA, Switzerland
Siltronic AG, Germany
DaimlerChrysler Research Centre, Germany
STMicroelectronics N.V., Switzerland
Deutsche Solar AG, Germany
StrataLight Communications, USA
EADS Radio Communication Systems GmbH und
SUSS MicroTec Test Systems GmbH, Deutschland
Synergy Microwave Corporation, USA
Co. KG, Germany
Enpirion Inc., USA
Synergy Microwave Research GmbH, Teltow
Freescale Semiconductor, Germany
Tanner Research Inc., USA
Fundacion Robtiker-Tenalia Technology Corp., Spain
Telefonica Investigacion y Desarrollo S.A.
Unipersonal, Spain
IMST GmbH, Germany
Infineon Technologies AG, Germany
Texas Instruments GmbH, Germany
InnoSenT GmbH, Germany
Thales Communication S.A., Switzerland
Institute for Solar Energy Research GmbH, Germany
Thales Electronic Engineering GmbH, Germany
Pulse Technologies, Russia
T-Systems Nova GmbH, Germany
KMSD Ltd. Kaunas Mixed Signal Design, Lithuania
VTT Electronics, Finland
KOTURA Inc., USA
Winfinity GmbH, Germany
lesswire AG, Germany
Wisair Ltd., Israel
MEDAV GmbH, Germany
XFAB Semiconductor Foundries AG, Germany
Melexis GmbH, Germany
ZMD AG, Germany
Merge Optics GmbH, Germany
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
67
Zusammenarbeit
und Par tner
Collaborators
and Par tners
Forschungsinstitute und Universitäten/Research Institutes and Universities
Australia Telescope National Faciity (CSIRO), Australia
Sino German Science Centre, Peking, China
CEA/LETI, France
Swiss Federal Institute of Technologies (ETH),
Delft University of Technology, The Netherlands
Switzerland
Denmark Technical University, Denmark
Technical University Bergakademie Freiberg, Germany
European University Viadrina of Frankfurt (Oder),
Technical University of Berlin, Germany
Germany
Technical University of Brandenburg, Cottbus,
Fraunhofer IIS, Germany
Germany
Fraunhofer ISE, Germany
Technical University of Catalonia, Spain
Freie Universität Berlin, Germany
Technical University of Darmstadt, Germany
Friedrich-Alexander University Erlangen-Nuremberg,
Technical University of Dresden, Germany
Germany
Technical University of Ilmenau, Germany
Georg-August University of Göttingen, Germany
Technion-Israel Institute of Technology, Israel
Georgia Institute of Technology Atlanta, USA
Tel-Aviv University, Tel-Aviv, Israel
Hahn-Meitner-Institute, Germany
TIMA Laboratory, France
Hangzhou Dianzi University, China
Tohoku University, Sendai, Japan
Humboldt Universität zu Berlin, Germany
University of Applied Sciences Wildau, Germany
IMEC, Belgium
University of Bristol, UK
Indian Institute of Technology, Kharagpur, India
University of Cambridge, UK
Institute for Infocomm Research, Singapore
University of Firenzi, Italy
Institute for Physical High Technology (IPHT), Jena,
University of Florence, Italy
Germany
University of Glasgow, UK
Institute of Computer Science, ICS-FORTH, Greece
University of Hamburg-Harburg, Germany
Institute of Microelectronics, Singapore
University of Karlsruhe (TH), Germany
Institute of Semiconductor Physics, Kiev, Ukraina
University of Kassel, Germany
Josef Stefan Institute, Slovenia
University of Konstanz, Germany
K. U. Leuven, Belgium
University of Limerick, Ireland
KTH Stockholm, Sweden
University of London, UK
Las Palmas de Gran Canaria University, Spain
University of Manchester, UK
London South Bank University, UK
University of Newcastle upon Tyne, UK
Ludwig-Maximilians-University of Munich, Germany
University of Nottingham, UK
Max Planck Institute of Microstructure Physics,
University of Oulu, Finland
Germany
University of Paderborn, Germany
National Electronics and Computer Technology
Centre, Thailand
University of Potsdam, Germany
University of Rom, Italy
National Technical University of Athens, Greece
University of Stuttgart, Germany
Politecnico di Torino, Italy
University of Toronto, Canada
Progress Microelectronics Research Institute,
University of Ulm, Germany
Moscow, Russia
University of Zielona Gora, Poland
RadioLabs, Italy
Victoria University, UK
RWTH Aachen, Germany
Zhejiang University, Zhedalu, China
Saint-Petersburg State University, Russia
68
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Zusammenarbeit
und Par tner
Collaborators
and Par tners
Brandenburgs Ministerin für Wissenschaft, Forschung und Kultur, Prof. Dr. Johanna Wanka, im Gespräch mit Schülern anlässlich der Übergabe
des Forschungspreises des Fördervereins „Freunde des IHP e.V.“ am 4. September 2004.
Brandenburg’s Minister for Science, Research and Culture, Prof. Johanna Wanka, conversing with pupils at the award-giving ceremony for
the research prize of the organization “Freunde des IHP e.V.” on September 4, 2004.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
69
Gastwissenschaftler und Seminare
Guest Scientists and Seminars
Gastwissenschaf tler
und Seminare
Guest Scientists
and Seminars
Gastwissenschaftler/
Guest Scientist
Institution/Institution
Forschungsgebiet/
Research Area
1. Dr. K. Washio
Hitachi Ltd., Central Research
Laboratory, Tokyo, Japan
Process Technology
2. Prof. O. Vyvenko
Saint-Petersburg State
University, Russia
Material and Diagnostics
3. Mr. V. Passi
University of Darmstadt,
Germany
Process Technology
4. Mr. B. Mongellaz
University of Bordeaux, France
Process Technology
5. Dr. A. U. Mane
Humboldt Research Fellowship
Material and Diagnostics
6. Mr. A. Hudyryev
Institute for Semiconductor
Physics, Kiev, Ukraina
Process Technology
7. Mr. O. Gromovyy
Institute for Semiconductor
Physics, Kiev, Ukraina
Process Technology
8. Mr. A. Chakravorty
Indian Institute of Technology,
Kharagpur, India
Process Technology
9. Prof. S. Bannerje
Indian Institute of Technology,
Kharagpur, India
Systems
Institute for Semiconductor
Physics, Kiev, Ukraina
Material and Diagnostics
10. Dr. V. Bukalo
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
71
Gastwissenschaf tler
und Seminare
Guest Scientists
and Seminars
Vortragender/Presenter
Institution/Institution
Topic/Thema
1. Dr. U. Wulf
Technical University of Brandenburg,
Cottbus, Germany
‘‘Other Projects about Quantum
Transport at the Chair of Theoretical
Physics of the BTU Cottbus”
2. Dr.-Ing. A. Willig
Hasso Plattner Institute for Software
Systems Engineering, Germany
“The Intermediate Checksum
Scheme”
3. Dr. K. Washio
Hitachi Ltd., Central Research
Laboratory, Tokyo, Japan
“Overview of Hitachi‘s SiGe
HBT/BiCMOS Technologies and Their
Applications”
4. Prof. P. Seegebrecht
University of Kiel, Germany
“MOS Tunnel Structures With the
Focus on Optical Properties”
5. Dr. P. N. Racec
IHP/BTU Joint Lab, Cottbus, Germany
“Transport Modelling in MIS-type
Nanostructures”
6. Mr. W. Hoenlein
Infineon Technologies Dresden, Germany
“Carbon Nanotubes – a Successor to
Silicon Technology?”
7. Mr. C. Hoene
Technical University of Berlin, Germany
“IP Telephony over Wireless LAN”
8. Mr. E. Hijzen
Philips Research Leuven, Belgium
“RF Device Research at Philips
Research Leuven”
9. Dr.-Ing. A. Festag
European Network Centre (NEC)
Heidelberg, Germany
“Mobile Internet”
10. Prof. C. Enz
CSEM SA, Neuchatel, Switzerland
“The EKV MOS Transistor Model for
Low-Voltage and Low-Power Circuit
Design”
11. Ms. D. Drachenberg
Technical University of Brandenburg,
Cottbus, Germany
“Examination of Antireflective
Coatings for 130 nm Technology”
12. Prof. A. Devi
Ruhr University of Bochum, Germany
“Precursor Engineering for Chemical Vapor Deposition and Atomic Layer Deposition of Advanced Functional Materials”
13. Mrs. S. H. Christiansen
Max-Planck-Institute for Microstructure Physics, Halle, Germany
“Future Silicon: Strained,
Flexible, Nano-structured”
14. Prof. A. Bestavros
University of Boston, Computer
Science Department, USA
“Exploiting the Transients of
Adaptation for RoQ Attacks on
Internet Resources”
15. Dr. med. G. Becher
FILT GmbH, Berlin-Buch, Germany
“Microelectronics and Semiconductor Technology for Medical Applications – Do Our Expectations Conform With the Possibilities and Do
We Even Know What To Expect ?“
16. Prof. S. Banerjee
Indian Institute of Technology
Kharagpur, India
“VLSI for Biomedical
Instrumentation”
72
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Gastwissenschaf tler
und Seminare
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Guest Scientists
and Seminars
73
Publikationen
Publications
Nachdrucke
ausgewählter Publikationen
Reprints of
Selected Publications
A 16-BIT CORDIC ROTATOR FOR HIGH-SPEED WIRELESS LAN
Koushik Maharatna1, Alfonso Troya2, Swapna Banerjee3, Eckhard Grass2, Miloš Krstiü2
2
1
Dept. of EE, University of Bristol, UK, [email protected]
IHP, Frankfurt (Oder), Germany, {troya, grass, krstic}@ihp-microelectronics.com
3
Dept. of E & ECE, IIT Kharagpur, India, [email protected]
Abstract – In this paper we propose a novel 16-bit low
power CORDIC rotator that is used for high-speed wireless
LAN. The algorithm converges to the final target angle by
adaptively selecting appropriate iteration steps while
keeping the scale factor virtually constant. The VLSI
architecture of the proposed design eliminates the entire
arithmetic hardware in the angle approximation datapath and
reduces the number of iterations by 50% on an average. The
cell area of the processor is 0.7 mm2 and it dissipates 7 mW
power at 20 MHz frequency.
Keywords – CORDIC, NCO, Synchronization, low power,
WLAN.
I. INTRODUCTION
OFDM-based high-speed Wireless LAN (WLAN) systems
are currently in the focus of research and development.
However, the hardware cost of such systems is quite high
and innovative techniques have to be used to design the
critical functional blocks in order to satisfy the timing and
power constraints as well as to minimize the overall circuit
complexity and cost. One such critical functional block is
the CoOrdinate Rotation DIgital Computer (CORDIC) that
can be used for the frequency offset correction of the input
data during synchronization at the receiver. In this case, the
forward rotation mode of the CORDIC is utilized which
essentially works as a Numerically Controlled Oscillator
(NCO). Though it offers an elegant solution, the classical
CORDIC algorithm has several shortcomings which
inspired many researchers to look into the development of
high-performance CORDIC algorithm and its efficient
implementation [1 – 6]. However, the algorithmic level
speed limit of CORDIC as well as the required scale factor
compensation are problems which restrict the application
range of this circuit.
In this paper we describe a novel CORDIC rotator that is
used for the synchronizer unit in a project that aims at the
implementation of single-chip modem for IEEE 802.11a
standard [7]. Though according to the specification of the
project we design a 16-bit CORDIC processor that can
operate in the forward operation mode only, the method can
be generalized for any arbitrary wordlength. In essence, the
current work is based on a scaling free CORDIC algorithm
proposed earlier by the authors [8, 9]. The CORDIC rotator
proposed here is virtually scaling free (needs a scaling by
1/√2 or 1) and has the convergence range over the entire
coordinate space. It converges to the target angle by
adaptively choosing the actually needed iteration steps only,
while skipping the other not actually needed iteration steps.
This adaptive selection does not have any impact on the
final scale factor. Based on this algorithm, we propose a
design of a low power 16-bit pipelined CORDIC rotator that
eliminates the entire arithmetic processing and subsequent
circuitry along the angle approximation (or z) datapath and
on an average saves 50% iterations without compromising
the accuracy. The rest of the paper is structured as follows:
Section II describes the theoretical formulation of the
algorithm while the VLSI implementation is described in
Section III. The performance evaluation is done in Section
IV and the conclusions are drawn in Section V.
II. THEORETICAL GROUNDWORK
In essence, this work is based on a scaling free CORDIC
algorithm proposed by the authors that eliminates the
problem of scale factor compensation [8, 9]. In this
algorithm the vector is rotated only in one direction in steps
of very small angles i so that the magnitude of the vector
remains preserved at each step of elementary rotation. The
angles i are expressed as,
sin( i)
i
= 2−i
(1)
With this consideration, the working equation of the scaling
free CORDIC at the ith iteration becomes,
ª xi + 1 º ª1 − 2− (2i + 1)
2− i
»=«
«
− (2i + 1)
«¬ yi + 1»¼ « − 2− i
1− 2
¬
z i+1 = zi − 2 −i
ºªx º
»« i »
»« y »
¼¬ i ¼
(2a)
(2b)
st
Because of the 1 order approximation used in equation (1),
the allowed values of elementary rotational index (iteration
index) i are,
¬(b − 2.585) / 3¼ = p ≤ i ≤ b−1
(3)
where b is the wordlength. Though this approach eliminates
the scale factor compensation problem, its convergence
range is very small. In this work we extend its convergence
over the entire coordinate space by employing a technique
called domain folding.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
75
Nachdrucke
ausgewählter Publikationen
Reprints of
Selected Publications
We first divide the first quadrant into four domains namely
A∈[0, π/8), B∈[π/8, π/4), C∈[π/4, 3π/8) and D∈[3π/8, π/2].
In each of these domains the target angle θ can be redefined
in terms of another angle φ bounded in the interval [0, π/8]
by the following equations,
independent of the number of iterations executed. On the
other hand, for the angles lying in domains A or D, no
scaling is required. We call this technique domain folding
since in this formulation all the domains are effectively
folded back to domain A.
θ =φ,
in domain A
(4)
θ = π/4 − φ ,
in domain B
(5)
θ = π/4 + φ ,
in domain C
(6)
θ = π/2 − φ ,
To enhance the convergence range of the scaling free
CORDIC to π/8, we propose the greedy algorithm shown in
Figure 1 which essentially selects only the absolutely
needed elementary rotational steps in an adaptive manner.
Rref in Figure 1 denotes a user-defined accuracy.
in domain D
(7)
Thus, the CORDIC rotator operation on an input vector
[x y]T in different domains can be expressed in terms of φ as
follows (considering clockwise rotation),
ª x fA º ªcos φ sin φ º ª x º
« »=«
»« »
¬« y fA ¼» ¬ − sin φ cos φ ¼ ¬ y ¼
(8)
ª x fB º
1 ª(cos φ + sin φ ) (cos φ − sin φ ) º ª x º
« »=
«
»« »
y
2 ¬ − (cos φ − sin φ ) (cos φ + sin φ ) ¼ ¬ y ¼
¬« fB ¼»
(9)
ª x fC º
1 ª(cos φ − sin φ ) (cos φ + sin φ ) º ª x º
« »=
«
»« »
y
2 ¬− (cos φ + sin φ ) (cos φ − sin φ ) ¼ ¬ y ¼
¬« fC ¼»
(10)
ª x fD º ªsin φ
cos φ º ª x º
« »=«
−
cos
φ
sin φ »¼ «¬ y »¼
y
¬« fD ¼» ¬
(11)
III. VLSI IMPLEMENTATION AND RESULTS
In principle, our design consists of three basic sections, viz.,
the sign/domain detection circuitry, the basic CORDIC
rotator having a convergence range [0, π/8], and the output
circuitry. The design specification for our system needs a
16-bit CORDIC rotator. In our formulation the maximum
target angle φ to be computed is π/8, which can be
expressed as 0001100100100010 with an error of O(2−16),
where we consider the definition of decimal 1 to be
0100000000000000. Thus, for representing the absolute
value of any angle lying in our modified convergence range
one can omit the 3 MSB and use the 13 LSBs. We use this
fact to reduce the arithmetic computation in the z datapath.
where xf* denotes the final vector resulting from a CORDIC
rotator operation with target angles lying in a certain domain
indicated by ‘*’.
Now denoting [x1+ y1+]T and [x1− y1−]T as the result of
CORDIC rotation for angles φ and −φ respectively,
equations (8) to (11) can be written as,
x fA = x1−
y fA = y1−
(12)
x fB =
1
[ x1+ + y1+ ]
2
y fB =
1
[ − x1+ + y1+ ]
2
(13)
x fC =
1
[ x1− + y1− ]
2
y fC =
1
[− x1− + y1− ]
2
(14)
x fD = y1+
y fD = − x1+
(15)
Hence, using the above equations, the CORDIC rotator
operation with target angles lying in any domain in the first
quadrant can be computed from the results of the CORDIC
rotation with the modified target angle φ (bounded in the
interval [0, π/8]). By exploiting the symmetry of the coordinate axes, this technique can be extended to carry out
CORDIC rotator operations with target angles lying in other
quadrants as well with minimal extra hardware overhead. As
a result, a CORDIC having a convergence range of [0, π/8]
is sufficient to cover the entire coordinate space. It is to be
noted that for target angles lying in domains B or C, we
require a fixed scale factor of 1/ 2 that is absolutely
76
Fig. 1. The proposed greedy algorithm.
A. Sign / Domain detection circuitry
We assume that the largest angle that can be assigned to the
primary input angle (z0) is within the range [0, 2π] and thus,
requires 18-bit representation. Any negative angle will also
fall in this range. Accordingly, the sign/domain detection
circuit has two 16-bit data input for x and y datapath and an
18-bit input for the z datapath. This circuit first detects the
sign (quadrant) and the domain in which the target angle lies
and applies the domain folding technique to derive a 13-bit
unsigned representation of the modified target angle φ. It
also generates two 2-bit signals called quad and domain that
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Nachdrucke
ausgewählter Publikationen
Reprints of
Selected Publications
characterize quadrant and domain of the original target
angle.
decimal 5. Note that the case in which all three MSBs are
‘1’ will never occur.
B. Basic pipelined CORDIC rotator
To keep the pipelined operation intact, we feed the
individual bits of the 13-bit unsigned representation of φ to
the appropriate elementary rotational sections as an enable
signal for that particular section through an array of shift
registers. The number of the shift registers is chosen in such
a manner that the appropriate section gets enabled at the
appropriate clock cycles. The complete architecture is
shown in Figure 3 where the dotted lines indicate the
concatenated elementary rotational stages. This arrangement
essentially mimics the search algorithm shown in Figure 1
and eliminates the comparison of zi with 2−i and Rref and the
associated computation of the new residual angle (zi+1).
Thus, the attendant hardware in the angle approximation
datapath can be omitted completely. It is to be noted that in
the conventional CORDIC algorithm this simple
arrangement for eliminating the z datapath cannot be
adopted directly since the target angle is approximated by
to-and-fro motion of the vector.
The elementary rotational section used here is shown in
Figure 2 [8], which is essentially derived from equation (2a).
For a pipeline implementation, each of these sections
requires two adders more compared to that of the
conventional CORDIC. However, for the elementary
rotational sections corresponding to i ≥ 7, a right shift by
(2i+1)-bit essentially results in a machine zero or retention
of the sign bit only and thus, the extra adders can be omitted
for those stages. The allowed values of iteration in the
present case are {4, 5, …, 15} (p = 4 from equation (3)).
However, a right shift by 15-bit once again results in the
retention of the sign bit only and thus for practical purpose
the i = 15 stage can be omitted. We will show later that this
does not significantly affect the accuracy.
In our implementation, we have used the i = 4 elementary
rotational stage six times whereas, the stages corresponding
to i = 5…14 are used once each. With this arrangement the
maximum angle that can be computed is 25°, therefore
covering our convergence range. To make the pipeline
completely balanced in terms of operation speed, we
concatenate
the
elementary
rotational
sections
corresponding to i = (7, 8), (9, 10), (11, 12) and (13, 14),
where the sections within the parenthesis form a single
pipeline stage. Thus, the basic CORDIC pipeline becomes
12 stages long, with the hardware complexity of each of
them being equivalent to four 16-bit adders. The signals
quad and domain are transferred synchronously between
two successive stages of the pipeline in a local register
transfer manner. These signals act as a token attributed to
the data in different sections of the pipeline carrying the
information about the initial quadrant and domain of that
particular data.
As it has been mentioned earlier, in this algorithm we
approach the target angle by rotating the vector in one
direction only. Thus, in essence, we are approximating the
final target angle as a pure summation of 2−i. As a result, the
appropriate rotational sections to be activated for a
particular target angle have a one-to-one correspondence
with the position of a logic ‘1’ in the 13-bit unsigned
representation of φ. As an example, let us consider φ = 20°
(0.349 radian). The unsigned representation of this angle is
1011001010111. To achieve this target angle, the rotational
sections to be activated are governed by the algorithm
described in Figure 1. In the present example these are i = 4,
4, 4, 4, 4, 5, 8, 10, 12, 13 and 14, whereas the deactivated
elementary rotational sections are simply bypassed. The
number of active i = 4 stages is obtained after decoding the
first three Most Significant Bits (MSB) in φ (12th, 11th and
10th bits). Hence, the combinatorial logic shown in Figure 3
is a simple digital decoder. In the previous example, we
found the first three MSBs to be 101, which corresponds to
Fig. 2. The elementary rotational section.
Fig. 3. The architecture of the basic CORDIC rotator.
C. The output unit
The output unit consists of two fixed scaling units of 1/√2
and two adder/subtractors according to (13), (14). The
scaling unit is realized using a shift-and-add technique and
requires five adders each, i.e. 2–1/2 = 2–1 + 2–3 + 2–4 + 2–6 +
2-8 + 2–14. Thus, the overall hardware complexity of this unit
is 12 16-bit adders. Depending on the quad and domain
signals, this unit assigns the sign, and either scales the data
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or passes it to the primary output registers. All the
operations in this unit are completed in one clock cycle.
The complete processor is modeled in VHDL and is
synthesized using IHP 0.25 µm BiCMOS technology. The
cell area of the processor core occupies 0.7 mm2 which is
equivalent to 24.7 k inverter gates in this technology. After
layout, the silicon area is 0.9 mm2. To our knowledge, this is
the smallest pipelined CORDIC rotator reported so far. The
power dissipation estimated by the Synopsys Design
Analyzer tool at the intended 20 MHz operation frequency is
7 mW. The latency of the processor is 14 clock cycles and
the throughput is 1 set of results per clock cycle. These
figures show that the processor consumes little silicon area
and is suitable for high-speed low power applications. The
layout of the processor core is shown in Figure 4.
[0, π/8]. On an average, the proposed processor saves 50%
computations. The worst-case iteration number is 15, which
occurs for the angle 21.482°.
Fig. 5. Required iterations for angles in range [0, π/8].
C. Accuracy
The error in the x and y datapaths is plotted in Figure 6.
Here, the actual VHDL model is compared with a Matlab
model of an ideal CORDIC. Figure 6 shows that the worstcase error in the x and y datapaths occurs at the 11th bit
position which is similar to that of the conventional
CORDIC having 16-bit wordlength.
Fig. 4. The layout of the CORDIC rotator core.
IV. PERFORMANCE EVALUATION
A. Area
The silicon area of the proposed design compared to some
existing designs is shown in Table 1 considering 16-bit
implementation. To make the comparison uniform, the
scaling circuitry is not considered here, since it is not
reported in [4] and [5]. It can be seen clearly that the
hardware requirement of the proposed one is less than the
others. It is also evident that the hardware cost of the
complete architecture is 22% less in terms of adders and
about 53% less in terms of registers compared to that of the
conventional CORDIC.
Table 1
A comparison of the proposed processor with some other
similar processors (16-bit implementation).
D. Power
The complete elimination of the z datapath in conjunction
with the reduction of the total number of iterations makes
the proposed scheme highly suitable for low power
applications. This fact is also reflected in our synthesis
results which show that the proposed processor consumes 7
mW power at 20 MHz operating frequency and 2.5 V power
supply.
# full adders
# registers
768
768
Dawid [4]
1,280
1,984
E. General discussions
Antelo [5]
896
1,632
Proposed
768
533
Though the proposed CORDIC algorithm eliminates the
problem of adaptive selection of elementary rotation steps in
conjunction with keeping the scale factor virtually constant,
it also shows some drawbacks. Hence, the algorithm
proposed here requires a variable number of iterations
depending on the final target angle. Though the processor is
primarily optimized for a high throughput pipeline structure,
Conventional
B. Number of iterations
Figure 5 shows the required number of iterations for a
pseudo-random sequence of target angles in the range
78
Fig. 6. Bit error position: a) x datapath; b) y datapath.
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the variable number of iterations incurs problems, when
using the algorithm in the feedback mode, i.e. not pipelined.
In that case, the performance is governed by the worst case
delay and not by the average case delay. However, using
asynchronous design or a Globally Asynchronous Locally
Synchronous (GALS) methodology, one can once again get
the advantage of average case performance even in the
feedback mode. In the synchronous mode, though the circuit
operates with the worst case delay, still power saving could
be quite significant.
Another problem in the proposed scheme is that the
selection of the largest elementary angle depends on the
wordlength (equation (3)). This angle becomes increasingly
smaller as the wordlength increases. Consequently, one
needs to incorporate more sections of this elementary angle
in the pipeline. As a result, the conventional CORDIC is
expected to outperform the proposed one in terms of
hardware requirement when the wordlength reaches 20-bit.
However, in that case, a hybrid scheme can be adopted to
bring down the hardware cost. One may use some
conventional CORDIC iteration (only unidirectional) to
bring down the residual angle within the range of the scaling
free CORDIC iterations and then employ the proposed
algorithm. In such a case, the scale factor compensation
circuitry required for those conventional CORDIC sections
has to be integrated into the corresponding elementary
rotational sections to avoid the generation of a final scale
factor and to maintain the virtually scaling free property of
the proposed algorithm. However, in general, hardware
implementations with 16-bit wordlength encompass a vast
application space and for that the proposed CORDIC rotator
shows significantly improved performance compared to the
conventional CORDIC.
V. CONCLUSIONS
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approximation datapath. This also makes the CORDIC
rotator operation faster and more economic. The hardware
cost of the complete architecture is 22% less in terms of
adders and about 53% less in terms of registers compared to
that of the conventional CORDIC. These features show the
advantage of the proposed CORDIC rotator compared to the
conventional CORDIC architecture. Moreover, the hardware
requirement for the pre-processing unit (sign/domain
detection circuitry) is very small compared to that used for
the other argument reduction techniques. The reduction of
area and the arithmetic computation suggests that the power
efficiency of the proposed structure is better than the
conventional CORDIC.
Based on this algorithm, a 16-bit pipelined CORDIC
processor core is designed using IHP in-house 0.25 µm
BiCMOS technology. The measurement results show that
the processor consumes little silicon area and is suitable for
high-speed low power applications. Currently, this CORDIC
processor is used as part of the Baseband Processor core in a
project aiming to design a single-chip wireless modem
compliant with the IEEE 802.11a standard [7].
REFERENCES
N. Takagi, T. Asada and S. Yajima, “Redundant
CORDIC methods with a constant scale factor for sine
and cosine computation”, IEEE Trans. Comput., vol. 40,
no. 9, pp. 989 – 995, Sept. 1991.
[2] J. A. Lee and T. Lang, “Constant-factor Redundant
CORDIC for Angle Calculation and Rotation”, IEEE
Trans. Comput., vol. 41, no. 8, pp. 1016 – 1025, Aug.
1992.
[3] J. Duprat and J. M. Muller, “The CORDIC Algorithm:
New Results for Fast VLSI Implementation”, IEEE
Trans. Comput., vol. 42, no. 2, pp. 168 – 178, Feb. 1993.
[1]
[4] H. Dawid and H. Meyr, “The differential CORDIC algorithm:
In this article, we present a novel algorithm and architecture
of a special rotational CORDIC processor that operates only
in the circular coordinate space and has an unlimited angular
convergence range. The algorithm adaptively selects the
appropriate iteration steps and thus, converges to the target
angle executing a minimum number of iterations. On an
average, the number of iterations in the proposed method is
about 50% less compared to that of the conventional
CORDIC processor without compromising the accuracy.
The novel property of the proposed algorithm is that, unlike
the conventional and previously reported CORDIC, the
adaptive selection of the iteration steps has no influence on
the final value of the scale factor (1 or 1/√2 depending on
the target angle). Thus, unlike the previously published
CORDIC rotator architectures, in our scheme, it is possible
to bypass the actually not needed iteration steps while
keeping the scale factor virtually constant.
Another novel feature of our algorithm and architecture is
that in this scheme it is possible to eliminate all arithmetic
computations and associated hardware in the angle
[5]
[6]
[7]
[8]
[9]
Constant scale factor redundant implementation without
correcting iterations”, IEEE Trans. Comput., vol. 45, no. 3, pp.
307 – 318, March 1996.
E. Antelo, J. D. Bruguera and E. L. Zapata, “Unified mixed
radix 2-4 redundant CORDIC processor”, IEEE Trans.
Comput., vol. 45, no. 9, pp. 1068 – 1073, Sept. 1996.
A. Madisetti, A. Y. Kwentus and A. N. Willson, “A 100 MHz,
16-b, direct digital frequency synthesizer with 100-dBc
spurious-free dynamic range”, IEEE J. Solid-State Cir., vol. 34,
no. 8, pp. 1034 – 1043, Aug. 1999.
M. Krstic, A. Troya, K. Maharatna and E. Grass, “Optimized
Low-Power Synchronizer Design for the IEEE 802.11a
Standard”, in Proceedings of the IEEE ICASSP’03, Hong
Kong, P.R. of China, vol. II, pp. 321 – 324, April 2003.
E. Grass, B. Sarker and K. Maharatna, “A Dual Mode
Synchronous/Asynchronous
CORDIC
Processor”,
in
Proceedings of the 8th IEEE International Symposium on
Asynchronous Circuits and Systems, Manchester, U. K.,
pp. 76 – 83, April 2002.
K. Maharatna, A. S. Dhar and Swapna Banerjee, “A VLSI
Array Architecture for Realization of DFT, DHT, DCT and
DST”, J. Signal Processing, vol. 81, pp. 1813 – 1822, 2001.
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THE SYSTEMC BEHAVIORAL MODEL OF IEEE 802.15.3
MAC PROTOCOL – DESIGN AND PROFILING
Jerzy Ryman, Daniel Dietterle, Kai Dombrowski, Piotr Bubacz*
IHP Frankfurt (Oder), Germany
*University of Zielona Góra, Poland
[ryman | dietterle | dombro]@ihp-microelectronics.com
[email protected]
Abstract: This paper summarizes our work on a SystemC model of the IEEE 802.15.3
medium access control (MAC) protocol. The starting point is our widely tested SDL
model of this protocol. The final goal of our work is an implementation of this protocol as
an embedded system. The SDL model does not provide any realistic information on
performance/resource consumption, which is required for hardware/software partitioning.
That leads us to SystemC as a step between the SDL behavioral model and our
implementation – it provides more realistic performance information and allows modeling
the hardware and software parts of the system. The complete SystemC model was
profiled to make hardware/software partitioning decisions. Copyright © 2004 IFAC
Keywords: System design, wireless protocols, SystemC, IEEE 802.15.3, hardware/
software partitioning, co-design, untimed functional modeling, SDL.
1. OVERVIEW
First, we will present the purpose of this work, then
briefly describe the IEEE 802.15.3 standard and
Specification and Description Language (SDL) used
to design the initial model. Then we will describe the
basic concepts introduced in this work. Next we will
describe our experiences with profiling and finally
we will conclude our paper and show possible future
work.
2. THE PURPOSE OF THIS WORK
Our goal is to design a low-power wireless
communications system for mobile battery-powered
devices and sensors. It shall provide transmission of
asynchronous data, as well as audio and MPEG-1
encoded video streams. In other words, the
communication system must provide a data
throughput of 3-5 Mbps and guarantee quality of
service (QoS). We found the IEEE 802.15.3 standard
fulfills our requirements. After having designed a
working SDL model the next step was to create
something in between the solely abstract behavioral
model and the target implementation. We decided to
use SystemC as a promising system description
language. It allows avoiding the standard waterfall
80
design scheme, using rather an almost seamless way
from the behavioral model to synthesizable final
code. While the Telelogic Tau SDL tool (Telelogic,
2003) allows the generation of C code from the
model, the result is inefficient (because of big
overhead) and hardly understandable code (very long
and hard to recognize names, all code in large file).
Such code is hard to optimize. In contrast, the
SystemC framework inherits all advantages of C++,
making it a viable system description language. The
code, while requiring time and effort to create, can
easily be understood, debugged, profiled and
optimized. There are also many ways to create the
final software part of the system using an available
real-time operating system. As for the hardware part,
available tools for converting SystemC to
synthesizable code seem to be not mature enough
such that manual creation of VHDL code is
unavoidable. After design, the system was tested and
profiled to find the most time consuming
modules/functions and consider system partitioning
eventually.
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The CAP can be used to communicate commands
and/or asynchronous data using the CSMA/CA1
contention scheme.
3. THE IEEE 802.15.3 STANDARD
3.1. General structure.
The standard (IEEE, 2003) provides a specification
for the Physical (PHY) and Medium Access Control
(MAC) layer for high-speed Wireless Personal Area
Network (WPAN). WPANs are used to convey
information over relatively short distances (up to
10m) among relatively few participants. Unlike
wireless local area networks (WLANs) personal
networks involve little or no infrastructure. This
allows small, power efficient, inexpensive solutions
to be implemented for a wide range of devices. The
standard differentiates 4 top-level blocks as shown
below.
During CTAP the TDMA2 scheme is used (PNC
makes assignments in beacon frame). There is also
one specific type of CTA block: Management CTA
(MCTA), which is used for communications between
the DEVs and the PNC.
3.3. Network topology.
The base topology is defined as a piconet –
a collection of one or more logically associated
devices (DEVs) that share a single identifier with a
piconet coordinator (PNC) – an entity that provides
time allocation, synchronization, association etc. The
basic piconet containing PNC and two devices is
shown below.
PNC/
DEV
data
beacon
data
The PHY and MAC layers have communication
interfaces called Service Access Points (SAP). The
interface between data and control paths is not
defined and therefore left to up to the implementer.
SAPs are also only a set of commands that have to be
implemented leaving the details up to the designer.
Power management is an important part of the
standard and is based on 3 sleep modes and power
level control. The standard provides also the
capability for encryption (security).
3.2. The superframe.
This is the base time division in the protocol. It has a
length set by the PNC (0 – 65535ms) and is
composed of 3 parts:
- beacon – generated by the PNC,
- contention access period (CAP),
- channel time allocation period (CTAP).
Superframe #m
data
beacon
DEV
DEV
Fig. 1. Top-level system view.
Superframe #m-1
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Superframe #m+1
Channel Time Allocation Period
Beacon Contention
Access MCTA MCTA CTA
CTA ... CTA
#m
Period
1
2
1
2
n
Fig. 2. Superframe.
Beacon is the time when the beacon frame is being
broadcast by the PNC. This specific frame contains
a complete set of information about the current state
of the piconet, channel time allocation (CTA) and
other piconet crucial data and is received by all
active piconet devices. It is used also to synchronize
all devices.
Fig. 3. Basic piconet.
3.4. Data flow.
The MAC Service Access Point defines Service Data
Units (SDUs) as the base unit of information. On
PHY level the base data unit is a frame defined as a
format of aggregated bits that are transmitted
together in time. SDUs can be spread over multiple
frames depending on time available for transfer, and
current data rate. Standard data rates are: 11, 22
(default), 33, 44, and 55 Mbps3. There are two base
data types – asynchronous and isochronous. The
latter is used for time critical, continuous applications
– for example audio or video streams. There are three
possible acknowledgement policies: no ack,
immediate ack, and delayed ack (can be used only for
streams).
1
Carrier Sense Multiple Access/Collision Avoidance: each
device listens to the signal level to determine when the
channel is idle. Then it waits for a random amount of time
before trying to send a packet. After a while, the device
senses the signal level again and if the channel is free, the
packet is sent. If the channel is busy, the time interval
before the next attempt is increased.
2
Time Division Multiple Access: devices can transmit data
only in time slots assigned to them. During time slot only
one device is allowed to transmit.
3
There is also an IEEE workgroup 802.15.3a that is
looking into extending this standard to use with Ultra
Wideband (UWB) for estimated data rates up to 1Gbps.
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4. SDL LANGUAGE AND SDL MODEL
4.1. SDL language
SDL is an internationally standardized (ITU-T, 1999)
language for specifying and describing systems. It is
a formal language, which means that it is possible to
analyze
and
interpret
SDL
descriptions
unambiguously. It can be represented in graphical
and textual descriptions. SDL has been widely used
by telecommunications engineers and standards
organizations for protocol specification, high-level
system specification, prototyping, design, and
testing.
The system behavior in SDL is based on
communicating extended finite state machines that
are executed concurrently. State machines are
represented by SDL processes. Processes
communicate with each other and the system
environment by exchanging asynchronous signals
that may carry any number of parameters. SDL also
provides timers that can be configured to generate
signals at defined points in time. Each process in an
SDL system contains a FIFO (First-In-First-Out)
input buffer (with infinite space) into which the
received signals are queued. Signal reception triggers
a state transition.
available elements: SystemC native elements
(modules, threads and events) and the SPACE
platform (Chevalier, et al., 2003). The SPACE is
a system providing both untimed and timed
functional (UTF/TF) simulation. The untimed
functional simulation is based on a simple connection
of many user modules. It does not increase the
simulation time on communication between modules.
That’s why we decided to use similar modularity,
and a specific communication scheme. The timed
functional (TF) simulation is based on an RTOS
running on the instruction set simulator (ISS) so it
provides real (or close to real) clock-based timing
results.
The reason why we decided to create our own system
instead using the available one is to simplify the
transition of the model from SDL to SystemC. We
decided to implement only the untimed functional
simulation without RTOS/ISS (but with possibility to
introduce them later).
The platform keeps the SystemC advantages,
provides good verification environment and easy way
to convert the model to use it with real time operating
systems (if it contains event-driven threads).
The important matter for us is a specific feature of
SDL called save symbol (Olsen, 1994). It is used to
notify the scheduler not to process the specified
signal(s) immediately but to keep them for future
processing.
Fig. 4. System overview
4.2. SDL model
5.2. Communication concept.
The object-oriented SDL model (Dietterle, et al.,
2004) was a base for creation of our SystemC model.
It contains also a simplified PHY layer for testing
purposes. While being functionally correct (that was
checked in many tests), the code generated from it is
inefficient (i.e. data processing algorithms are slowed
down) because of the overhead (for communication
and scheduling) introduced by the SDL runtime
environment. It is very hard to process such code
further for debugging, profiling, or any other
purpose. That was the reason for creating the
SystemC model.
This is one of the main problems in modeling system
containing both software and hardware parts especially if we want to keep partitioning flexibility.
While our model is much closer to the software than
hardware, we wanted to have the flexibility to change
part of the modules to a more hardware-like
description. Therefore, we decided to create our own
scheme of communication based on signals carrying
data between modules. The modules communicate
solely through those signals except for the few cases
when direct access to memory contained in specific
modules is necessary.
5. DESIGN PRINCIPLES
Signals.
Base signal contains target and source
module identifier and command identifier. It is parent
class for children that contain additionally all
necessary parameters.
5.1. SystemC and design concept.
SystemC is a C++ class library and a methodology
for designing models of software algorithms, and
hardware architecture on system-level. It is offering
wide abstraction level possibilities – from the pure
C/C++ functional description to RTL level (Open
SystemC Initiative, 2003). The optimal design flow
methodology is to begin with a behavioral model
based on a barebone allowing seamless (or almost
seamless) flow to less abstract level. We decided to
create our own platform (barebone) based on two
82
Adapters. The signals incoming to modules ar not
accepted unconditionally. Different states of the
module (state machine) have different signals
allowed to be consumed. In out concept this is
specified by a list of accepted signals. That list is
generated by a module and passed to assigned
adapter. The adapter checks internal signal queue for
presence of the signals from the list and if it finds it
sends the signal to the module.
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The adapter also provides signal prioritization with
two levels: normal and high priority. High priority is
used for the reset signals. It is used to reinitialize the
whole device in the same time (to avoid the
hazardous situation that one device is already after
reset and the other is still few signals in the queue
before reset signal and have to process them).
Communication manager. This is the part joining
all adapters into one system and providing the signal
flow between them.
Module interface. In our platform, we provide the
interface for the modules containing the model
functionality.
It is called Comm_Man_If and
provides write and read methods for signals.
Modules are designed to keep the SDL design – they
are extended finite state machines. They contain a
specific function called event_loop() that is declared
as a SystemC thread. This function provides event
driven sensitivity to incoming signals and/or timer
events. In addition, it submits the accepted signal list
to the connected adapter and reads signals from it.
Based on signal contents proper function of the
module is called with parameters from the current
signal and the module's current state.
Signals flow. The communication looks like this:
- source module sends the prepared signal to
its adapter using write function,
- adapter sends it to the communication
manager,
- communication manager retrieves target
identifier from signal and sends it to the
correct adapter,
- target module's adapter receives signal,
stores it in the queue and notifies the
module's event loop that it has a new signal,
- target module decides when it is ready and
calls read function providing the current
accepted signal list to the adapter – if
adapter finds signal from the list in its queue
it returns the pointer to it (otherwise it
returns null).
6. MAC PROTOCOL DESIGN
Our model is split over multiple modules – each
providing its own functionality. The modules are
gathered into bigger entities called blocks. While the
MAC data path is not very complex and contains
only 7 modules combined into one block, in
the MLME we decided to distinguish 3 sub-blocks:
- Transport Engine – responsible for close
cooperation with the data path (data
management),
- Piconet Operation – responsible for all
actions connected with joining, managing,
or leaving the piconet,
- Request Handler – responsible for dealing
with commands coming from higher layers
through the MLME SAP.
Also, in some cases, we decided to separate the
functionality solely used by the PNC and the client
device (piconet member). That gives us the
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opportunity to model also simplified devices not
capable of acting as PNCs (such devices are allowed
by the standard). For example, the time slot
allocation for the channel time allocation period
(CTAP). The CTAServer is responsible for gathering
time slot requests from all devices and to provide
time slot assignment during the beacon generation.
The CTAClient generates time slot requests that are
sent do the PNC and interprets the answer.
Because the system doesn’t have a shared memory
block the whole used memory is declared inside the
modules. TxSDUPool and RxFramePool are the two
main owners of memory. In TxSDUPool we store the
SDUs to transmit. RxFramePool gathers incoming
frames and joins them into the complete SDU.
The MAC provides CRC generation/checking, which
is tested by the introduction of some random errors in
our airlink model. To speed up simulation execution
time we reduced the model complexity by leaving
out encryption (it is optional in the standard).
We can very easily test our model in different
configurations with different number of stations and
different parameters. The first test we made was with
2 devices – one of them acting as PNC and the other
as device that joins the piconet (DEV). We have
tested all functionality in this configuration. Then we
switched to the model containing 6 devices.
7. PROFILING
As mentioned before in this paper, the simulation
does not provide any data about time spent during the
function's execution. That is the reason why we
profile our system – to get the time effort spent on
each module/ function. For profiling we decided to
use Intel V-Tune tool. It provides timing information
and dependencies between functions.
The two most relevant time-consumption parameters
are: self-time (the time spent in function alone) and
total time (also including called sub-functions). In
the profiling output we can observe what is most
important to us – timing results of all interesting
functions – of course those results have to be
properly understood in the context. I.e. some
functionality that requires response from another
module is often split into two or more functions. Also
some functions contain small internal state machines
and are called a few times for complete execution. In
the output we can see different stations separately –
the problem being that it is not always clear as to
which station we should assign the output result – the
naming does not provide such information, so we
have to analyze it to find that out.
The collected data plus additional information about
architectural and performance differences between
system
used
for
simulation
and
final
processor/system can give us estimation of fulfilling
time constraints based on required data rate. We can
distinguish two base types of time consumption from
the point of view of our modules – lets call them
static and dynamic.
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7.1. Static vs. dynamic time consumption.
That type of time consumption is caused by initial
creation and destruction of system. Also thread
initialization is a constant part of the simulation.
While they are slightly different for each simulation
run the time differences are relatively small and we
can omit them. To measure the static time
consumption we run an idle testbench.
The dynamic time consumption is the most
interesting parameter. This type of time consumption
is caused by the system functionality. To obtain this
data we run a simulation testbench with the
functionality we want to measure and compare the
result with that from the idle testbench. Some
functions have some platform-related overhead. We
can remove this overhead by analyzing the functions
called by them.
7.2. Example profiling results.
Here we will present example results from the
testbench containing two devices, with one of them
acting as a PNC, and the other one as a member of
the piconet (DEV). The example testbench executes
the following activities: PNC initialization, DEV
association to the piconet and small (2000 bytes)
isochronous stream being transmitted from the DEV
to the PNC. The simulation is run for 2 seconds of
simulation time (the program execution time is
shorter).
Table 2 TxFrame functions time results
Thread / function
Calls Time self/total
Main simulation:
scalar del. destructor
~TxFrame
TxFrame
2
2
2
2 / 78
75 / 76
321 / 580
PNC:
event_loop
phy_data_confirm
phy_tx_end_confirm
phy_tx_start_confirm
transmitFrame_request
transmitFrame
1
2055
48
48
48
1
10916 / 18228
897/897
1/1
19/19
21/21
5075 / 16694
DEV:
event_loop
phy_data_confirm
phy_tx_end_confirm
phy_tx_start_confirm
transmitFrame_request
transmitFrame
1
2133
14
14
14
1
10699 / 18927
2112/2112
0/0
5/5
6/6
5023 / 16544
profiler). The main simulation thread contains
construction and destruction of both station TxFrame
modules. Then we have 2 stations – we can observe
that most of consumed time is spent in 2 functions –
event_loop and transmitFrame. That is because these
functions are both defined as SystemC threads –
that’s why they are called only once. The part of time
spent in these functions is SystemC scheduling
overhead. It is mostly the thread initialization – and
that part we can see in the idle testbench. The rest is
execution time. The time difference between the total
and self-time has to be interpreted by looking at the
called sub-functions. In the event_loop it is mostly
communication effort. In the transmitFrame it is
CRC calculation.
The remaining functions are usual C++ functions
(except of use of event notification to drive the
transmitFrame thread). The phy_data_confirm is
called on every incoming byte – that’s why the
number of calls is much higher. The
transmitFrame_request, phy_tx_start_confirm and
phy_tx_end_confirm are called on only once per
frame so thay are called not so often. As we can see
the time spent in these functions is much smaller than
the one in threads. 7.3. Interpretation.
We can clearly see that most of the time here is spent
on scheduling overhead but we can quite easily get
the real functionality time consumption. For the task
of finding the best hardware/software partitioning we
don’t need the absolute time results – it is enough to
have relative time consumption, therefore we don’t
have to go into the exact time calculations. But
always we have to interpret the data in the
platform/module context – otherwise we can get
misleading conclusions.
8. CONCLUSION AND FUTURE WORKS
8.1. Conclusion.
We can clearly see that the chosen methodology
results meet our expectations. The model can be
tested and profiled for very detailed output results.
The design methodology (platform) can be used in
the future to model other systems, or even to create
some tool for automatic conversion from SDL to
SystemC. The testing proved our model correctness.
Profiling information provided us good base to make
hardware/software partitioning decisions.
In table 2 we can observe how many times each
function was called and the self-time and total time
(both in µs) spent on the TxFrame functions. We can
distinguish three elements – main simulation and two
SystemC modules (they are seen as fibers4 in
4
Lightweight object that consists of a stack and a register
context and can be scheduled on various threads.
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8.2. Future works.
For enhancing the design we plan to introduce all (3)
power saving modes into our system. We are testing
different real-time operating systems for integration
in our final embedded system. The part of the MAC
that will be ported into hardware has to be designed
in VHDL language. We will test different approaches
to “push” code from presented model to the final
software part. That will require some modification
because we want to avoid context switching between
modules, as it is present in current model. So
SystemC modules will in the end become just C++
classes and communication will change from signals
to simple function calls (except the interface to
hardware).
REFERENCES
Chevalier J., O. Benny, M. Rondonneau, G. Bois,
E. M. Aboulhamid and F.-R. Boyer (1972).
SPACE: A Hardware/Software SystemC
Modeling Platform Including an RTOS.
www.grm.polymtl.ca/circus/mwc/2003_11/
Dietterle D., I. Bababanskaja, K. Dombrowski, R.
Kraemer (2004). High-Level Behavioral SDL
Model for the IEEE 802.15.3 MAC Protocol.
In: Proc. of the 2nd International Conference on
Wired/Wireless
Internet
Communications
(WWIC).
IEEE 802.15.3 Workgroup (2003). Part 15.3:
Wireless Medium Access Control (MAC) and
Physical Layer (PHY) Specifications for High
Rate Wireless Personal Area Networks
(WPANs).
ITU-T (1999). ITU-T Recommendation Z.100
(11/99). SDL: Specification and Description
Language.
Olsen A., O. Faefgemand, B. Moller-Pedersen,
R. Reed, J.R.W. Smith (1991). Systems
Engineering Using SDL-92, chapter 3.7.5.
Elsevier Science, Netherlands
Open SystemC Initiative (2003). SystemC 2.0.1
Language Reference Manual.
www.systemc.org
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Proceedings of the 30th European Solid-State Circuits Conference
September 20 - September 24, 2004, Leuven, Belgium, pp. 83-86
60 GHz Transceiver Circuits in SiGe:C
BiCMOS Technology
Wolfgang Winkler, Johannes Borngräber, Hans Gustat, Falk Korndörfer
IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany
Phone: +49-(0)-335-5625-150 E-mail: [email protected]
Abstract
This paper presents the design and measurement of key
circuit building blocks for a high-data-rate transceiver in
the 60 GHz band. The adopted modulation scheme is
ASK for simple configuration with high data rate. The
circuits presented are: LNA, oscillator, mixer, modulator
and demodulator. The circuits are fabricated in a
0.25 Pm SiGe:C BiCMOS technology.
1. Introduction
Traditionally, multimedia content is transferred with
wired transmission systems. Because of the limited data
rates, conventional WLAN systems cannot take over this
task. That’s why new wireless transmission systems with
data rates > 150 Mb/s are under investigation [1]. In [2] a
wireless transceiver module at 60 GHz is presented
showing a data-rate as high as 1.25 Gb/s. The chip set
consists of different MMICs based on 0.15 Pm
AlGaAs/InGaAs heterojunction FET technology.
For future low-cost systems it is required to realize the
full transceiver in a silicon-based technology on a single
chip or at least with a low chip-count. With the modern
CMOS, bipolar and BiCMOS technologies developed in
the last few years it seems certain to make true this goal
in short term [3].
This paper presents the design and measurement of key
circuits for the implementation in a high data-rate
60 GHz transceiver. At the present state, the circuits are
completed for on-wafer measurement.
analog part of the system without having to deal with
complexity, throughput and power consumption of
high-data rate digital processing.
- The bandwidth available in the 61 GHz ISM band is
500 MHz. Thus, bandwidth efficiency is less important
compared to lower frequency bands.
- In a bandwidth-efficient modulation scheme like
OFDM, the A/D converter (ADC) is a major problem.
With the required low power consumption and
throughput in mind, it is difficult to design an ADC
that would suit the system needs.
In summary, ASK seems well suited for a firstgeneration 60 GHz transceiver, due to simplicity and
power efficiency. Later implementations will certainly
make use of more sophisticated modulation schemes.
The transmit path of the transceiver consists of a
61.25 GHz fundamental mode oscillator, a switch and a
power amplifier. Between the modulator and the power
amplifier a filter is inserted to reduce spurs. The receiver
path consists of a low noise amplifier (LNA), a mixer, a
56 GHz oscillator, a variable gain amplifier and an ASK
demodulator. The circuit blocks in dashed boxes in
Figure 1 are described in this paper.
.
2. Circuit Design
A. Transceiver Architecture
Figure 1 shows the block diagram of the proposed
transceiver. It is based on amplitude shift keying
modulation principle (ASK). The reasons for the
selection of this modulation technique are the following.
- ASK is a very simple modulation scheme allowing
designing and demonstrating a 60 GHz transceiver in a
relatively short time-scale. It allows focusing on the
86
Figure 1 : Transceiver block diagram
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B. Low Noise Amplifier
The three-stage LNA circuit is shown in Figure 2 and
Figure 3. One task of the LNA design was to get
unconditional stability for both on-wafer measurements
and for the use of the amplifier in test board modules
together with the other receiver components. Especially
the use of bond wires for the connection of the ground
potential (and the associated inductance) causes serious
stability problems if a single-ended configuration is used.
That’s why all the stages are designed in differential
configuration. The input and output are trafo-coupled.
The transformer coupling is useful in two ways. First, it
acts as a balun for connection to a single-ended antenna.
Second, the primary and secondary windings of the
transformer are tuned to gat a bandpass characteristic.
With this, an additional input filter in the RX path can be
omitted and this function is integrated in the LNA.
The circuit of one single stage of the LNA is shown in
Figure 3. It is a differential stage with inductive load and
with matching network at the output.
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interference via the silicon substrate is reduced in
comparison to a single-ended version.
The diodes and resistors in the circuit are used to define
the operating point of the transistors. The tank is a
symmetric circuit of the Inductors L1 and the MIM
capacitor C1. The base-emitter capacitors CBE of the
bipolar transistor acts in parallel to the MIM capacitors
C1. For explanation, the tank can be divided into two half
circuits separated by the symmetry line shown in Figure
4. In operation, the oscillator-halves are working in the
odd mode, such that the outputs are 180º out of phase.
The nodes of the tank indicated by the symmetry line are
fixed at virtual ground for the fundamental tone.
The inductors L1 are designed as arms of a single loop of
metal layer 4 (Aluminium with 2 µm thickness and
10 µm width). The simulated inductance is 85 pH per
arm. The capacitor C2 is a varicap formed by an nchannel MOS device. In order to get a wide range of
capacitance variation the device is working in the whole
range from depletion to accumulation. The voltage for
frequency-control is applied to the n-well of the
structure. With VCtrl becoming more positive, the MOS
structure is driven into depletion and the capacitance will
be reduced. The output of the oscillator core is connected
to an amplifier in the case of the receive path. The
oscillator of the transmit path is directly connected to the
amplifier with switch (Figure 1).
Figure 2 : 60 GHz LNA.
Figure 3 : Circuit of one stage of differential LNA.
C. Oscillators
Figure 4 : Circuit of the LC oscillators used in the receive
and the transmit path.
D. Mixer
The transceiver architecture of Figure 1 requires two
oscillators working at different frequencies. One is for
the transmit path at the centre of the ISM band at
61.25 GHz. The other frequency in the receive path is the
transmit frequency reduced by the intermediate
frequency (IF). The circuit principle of both oscillators is
based on a modified Colpitts principle in a symmetric
configuration of negative-resistance type as shown in
Figure 4 [4]. With the symmetric circuit the signal
The mixer circuit is a balanced Gilbert cell with
symmetric LO and RF inputs. The differential output is
connected to the VGA giving the differential signal to
the demodulator.
E. ASK Modulator
The modulator circuit consists of bipolar transistors and
a MOS transistor (Figure 5). It is a symmetric common-
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base amplifier with the base connected to the drain of an
n-channel MOS transistor. The gate of the MOS
transistor is connected to the data input. With low
voltage level at the input the MOS transistor is switched
off and the common-base circuit acts as an amplifier
transferring the RF to the power amplifier. With highlevel at the input the MOS transistor is switched on and
the base-emitter voltage approaches zero. In this manner
the amplifier is switched off and the power amplifier
input is isolated from the oscillator. The advantage of the
circuit is the shielding function of the bipolar base region
so that a good isolation can be expected.
Figure 5 : RF switch for modulation of the RF signal.
3. Measurement Results
The circuits were fabricated in the IHP 0.25 Pm SiGe:C
BiCMOS technology. The bipolar transistors of this
technology have a maximum transit frequency fT of
200 GHz and also a maximum frequency of oscillation
fmax of 200 GHz. In the circuits mainly bipolar transistors
and passives were used. The only MOS transistor so far
is the switch in the modulator circuit. Figure 7 shows
photos of the presented circuits. The oscillators were
characterized using an on-wafer test-system with GSprobes. The supply voltage of the oscillators and mixer is
3V and the voltage of the switch, demodulator and the
LNA is 2.5 V.
b)
a)
F. Demodulator
The amplitude-shift keying demodulation uses a fullwave rectifier together with a lowpass filter (LPF)
corresponding to the maximum data rate of 1Gb/s. The
block diagram is shown in Figure 6. Full-wave
rectification is easily achieved using both differential
inputs. The diode function is implemented using highperformance transistors, resulting in wide input
frequency range (3-30GHz) giving large IF flexibility.
However, the summation is a differential-to-single-ended
conversion. To regenerate the differential mode, the
output of an additional common-mode block (CMB) acts
as the corresponding inverted signal. A subsequent
differential amplifier provides sufficient gain for bit
slicing.
c)
d)
e)
Figure 6 : ASK demodulator block diagram.
Figure 7 : Chip Photo of a) LNA, b) mixer, c) oscillator of
the receive-path, d) oscillator and switch in the
transmit-path, e) receiver test structure.
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The LNA was measured on wafer with a 110 GHz vector
network analyser. The maximum gain is 9.6 dB. The
gain-maximum is reached at 61 GHz, which is exactly
the target frequency of the requested ISM band (Figure
8). The LNA has a bandpass characteristic resulting from
the tuned transformers at input and output. With this
characteristic, no additional bandpass filter is needed.
Figure 10 : Tuning curve of the LC oscillator in the
receiver.
4. Summary and Conclusions
Figure 8 : Gain curves of the 60 GHz LNA.
The transmit path was measured by applying a
rectangular waveform to the data input of the modulator
while the integrated oscillator generates the RF power.
Figure 9 shows the output of the switch measured with
an oscillograph. The signal at the data input has a
frequency of 200 MHz. The output amplitude is
210 mVpp. The output frequency of the oscillator is
65 GHz. This frequency is too high in comparison to the
target of 61.25 GHz. A redesign of this oscillator is
required.
Key circuit blocks for 60 GHz high data-rate transceiver
system were successfully designed and fabricated in a
SiGe:C BiCMOS technology. The adopted modulation
scheme was ASK for simple configuration with high data
rate.
The measurement results show 9.6 dB gain of the LNA
at 61 GHz, 4 GHz tuning range of the oscillator in the
receiver with a centre frequency of 58 GHz and an ASK
modulator with good isolation properties and 210 mVpp
output voltage. Further measurements and a redesign is
in progress.
Acknowledgements
The authors acknowledge the IHP technology team for
chip fabrication and the modelling team for supplying
accurate models of the devices.
References
Figure 9 : Signal of the oscillator with switching the
output on and off.
The LC oscillator in the receive path has a tuning range
from 56 GHz to 60 GHz. The chosen IF frequency for
the VGA and the demodulator is 4 GHz. Figure 10 shows
the tuning curve of the VCO.
[1] P. Smulders, “Exploiting the 60GHz band for local
wireless multimedia access: prospects and future
directions,” IEEE Communications Magazine,
pp.140-147, Jan. 2002, pp. 118-121.
[2] K. Ohta et al., “Wireless 1.25 Gb/s transceiver
module at 60GHz band,” ISSCC Dig. Tech. Papers,
pp. 298-299, Feb. 2002.
[3] S. Reynolds et al., “60 GHz transceiver circuits in
SiGe bipolar technology,” ISSCC Dig. Tech. Papers,
pp. 442-443, Feb. 2004.
[4] W.Winkler et al., “60 GHz and 76 GHz oscillators in
0.25 Pm SiGe:C BiCMOS“, IEEE Int. Solid-State
Circuits Conf., February 2003, pp. 454-455.
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A Low-Parasitic Collector Construction for High-Speed SiGe:C HBTs
B. Heinemann, R. Barth, D. Bolze, J. Drews, P. Formanek, Th. Grabolla, U. Haak, W. Höppner, D. Knoll,
K. Köpke, B. Kuck, R. Kurps, S. Marschmeyer, H. H. Richter, H. Rücker, P. Schley, D. Schmidt,
W. Winkler, D. Wolansky, H.-E. Wulf, and Y. Yamamoto
IHP
Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
collector doping, reducing both the base-collector transit time
and the external base-collector capacitance (CBC). However,
conventional collector designs (Figs. 1b, c) consume more Si
area for the base-collector transition than it is needed to form a
low resistance current path from the active transistor to the external collector region. To address this issue, we developed a
new collector construction for high speed SiGe HBTs. Substantially reduced parasitic base-collector capacitances were
achieved by an undercut of the collector region (Fig. 1a). Using
different types of HBTs, we show peak fT values and CML gate
delays for both npn and pnp transistors that surpass the best in
class data reported so far (1), (3), (6).
Abstract
We present a new collector construction for high-speed
SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector
region. The impact of the collector module on RF performance
is demonstrated in separate bipolar processes for npn and pnp
devices. A minimum gate delay of 3.2ps was achieved for
CML ring oscillators with npn transistors featuring fT/ fmax
values of 300GHz/250GHz at BVCEO = 1.8V. For pnp devices
with fT/ fmax values of 135GHz /140GHz at BVCEO = 2.5V a
gate delay of 5.9ps is demonstrated. Further vertical scaling of
the doping profiles increases fT to 380GHz at BVCEO = 1.5V
for npn’s and 155GHz at BVCEO = 2.3V for pnp’s, but ring oscillator speed and fmax degraded.
Device Fabrication
To test the new collector module, we developed a bipolar
process that is shown schematically in Table I. This process is
based on our 0.25 Pm BiCMOS flow with elevated extrinsic
base regions (4). In this work, the final RTP step was changed
enabling a vertical scaling of doping profiles. On different wafers, npn and pnp transistors were produced in the same flow
by inverting the doping types. The key feature of the new collector design is a selectively underetched collector pedestal
(Fig. 1a). In Fig. 2, schematic drawings illustrate the fabrication of this module.
Introduction
The need for still higher device speeds has led to ingenious
technologies for SiGe HBTs that try to minimize internal transit times and parasitic charging times. Record fT/fmax values of
300GHz and above (1), (2) and very high circuit speeds, such
as ring oscillator gate delays below 4 ps (3), (4), (5) resulted.
Including the highest performance level, a selectively-implanted collector (SIC) is employed to provide a locally enhanced
Emitter Poly-Si
Emitter Poly-Si
SiGe Base
Collector Pedestal
SiGe Base
Base Poly-Si
Emitter Poly-Si
SiGe Base
Base Poly-Si
Base Poly-Si
SIC
SIC
SiGe base
Highly Doped Collector
Highly Doped Collector
a)
b)
Highly Doped Collector
c)
Fig. 1. Schematic cross-section of the novel HBT structure a) with selectively underetched collector pedestal compared to previous device structures with
differential b) and with selectively grown base layers c).
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Table I
SCHEMATIC FLOW OF THE BIPOLAR PROCESS.
Basic process flow
New collector module
Shallow trench isolation
Deposition and structuring of poly resistors
Deposition of nitride layer for CMP stop
Opening of HBT regions
High dose collector implant + RTA
Si epitaxy
Deposition of oxide/nitride layer stack
Hard mask structuring for pedestal etching
Forming pedestal spacers
Pedestal etching
Oxide fill and CMP
Nitride wet etching
HBT module
Implantation of collector contact regions
Salicide protection layer for resistors
Final RTA + Co salicidation
2 level Al metall.
After formation of shallow-trench isolation (STI), the collector module starts with the deposition of a first nitride layer
that serves later as polish stop for a chemical-mechanical polishing (CMP) step. A first resist mask is patterned to remove
the nitride layer over areas enclosing the transistor regions followed by the high-dose collector-well implant (Fig. 2 a). Next,
a layer stack consisting of epitaxially-grown low-doped Si, of
an oxide and a second nitride layer is deposited. Then, a second resist mask is applied to define a hard mask for the collector-pedestal etching (Fig. 2 b). In order to tailor the shape of
the pedestal, the Si etching is performed in two steps. In the
first step, the low-doped Si is removed by dry etching. Subsequently, a spacer is formed covering the side-walls of the hard
mask and of the etched Si step. In the second step, the collector
pedestal is undercut by a combination of dry and wet etching
exploiting the different etch rates of the high-doped and lowdoped Si layers. Finally, the collector pedestal is leveled by
CMP after filling up the etched regions with oxide (Fig. 2c).
After removing the CMP-stop layer, poly resistors are fabricated. Next, a nitride layer, protecting the poly Si resistors, is
deposited and structured to open the transistor regions. In the
following epitaxy step, a Si buffer layer, the SiGe:C base layer, and a Si cap layer are grown differentially. The following
process flow of the HBT module is performed as described in
(4), involving the formation of the emitter and the self-aligned,
elevated extrinsic base regions.
After removing the nitride protection layer, the fabrication is
completed with the following steps: implantation/anneal of
Deposition of protection layer for poly resistors
Opening of HBT regions
HBT epitaxy
Emitter window opening
Emitter deposition
Poly emitter structuring
Selective growth of elevated extrinsic base
Structuring base poly
Wet etch of protection layer
collector contact regions, applying a salicide blocking mask for
the poly resistors, cobalt salicidation, and structuring of two
metal layers.
Fig. 3 shows the novel collector structure as TEM cross-section in comparison with a schematic drawing. In contrast to
conventional constructions, the external, dielectrically-isolated
base layer has a single crystalline part on the isolation. This allows us to optimize the RF performance by varying the collector window enclosure of the emitter window largely relieved of
concerns arising from facet leakage or increasing RB.
Device Results
Gummel and output characteristics as well as fT(IC) and
fmax(IC) curves are shown for both types of HBTs in Figs. 4 6. Our extraction procedure for fT and fmax is outlined in Figs.
6 and 9.
Vertical scaling in combination with the new collector design has led to significantly improved fT values (Fig. 6) and
CML ring oscillator (RO) gate delays (Figs. 7, 8) compared to
our previous results. The base width is reduced due to the lower
thermal budget. Simultaneously, parasitic CBE is decreased because of a reduced indiffusion of the emitter doping. Furthermore, the high collector doping is shifted closer to the base.
E.g., for the npn HBT with peak fT=300GHz (Fig. 6) the total
CBC at VCB=0V is reduced from 3fF to 2.5fF compared to our
conventionally fabricated reference devices, despite a doubling
of the area specific base-collector capacitance. This is due to a
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Resist
Resist
CMP Stop Layer
SiO2
Si3N4
Fill Oxide
Spacer
Si
Collector Implantation
Highly-doped Collector
STI
Collector Pedestal
a)
b)
c)
Fig. 2. Schematic drawings of the novel collector structure after applying a) the 1st and b) 2nd mask of the collector pedestal module and c) after filling the
underetched collector pedestal with oxide and before CMP.
A further increase of the peak fT values was achieved for
both types of bipolar transistors (dashed lines in Fig. 6, npn:
300GHz -> 380GHz, pnp: 135GHz -> 155GHz) by shrinking
the deposited base layer thickness. For the npn an even more
aggressive collector profile was introduced in addition. However, the fmax values (see Fig. 6) and RO gate delays deteriorated. While in the pnp case, only a moderate degradation of
the minimum gate delay Wmin from 5.9ps to 6.0ps was observed, Wmin increased substantially in the npn case
(3.2ps ¯>3.8ps). In future, lateral scaling of the transistor dimensions assisted by the new collector design will help us to
balance fT and fmax also for higher fT values.
SiGe Base
Emitter
large reduction of contributions to CBC from the perimeter of
the device attributed to the new collector construction. The
high fT and low CBC are primarily responsible for the shorter
gate delays compared to our reference collector construction
(4). Further improvements of fmax and of the gate delay can be
expected for an optimized collector depletion width and a reduced RB.
Base Poly-Si
Collector Pedestal
a)
Emitter Si
Base Poly-Si
SiGe Base
b)
Conclusions
Compared to previously demonstrated concepts, the new
collector design achieves lower collector capacitances, while
maintaining low collector resistances and small collector-substrate junction areas. It supports heat dissipation due to the absence of deep trenches and a precise tailoring of the basecollector width for best RF performance. The new collector
module paves the way for very aggressive lateral scaling at
highest level of RF performance.
Acknowledgment
The authors thank the IHP pilotline staff for excellent support, F. Korndörfer for RF measurements, and G. Weidner for
TEM cross-section preparations.
Fig. 3. Cross-sections of the final HBT structure: a) schematic drawing
and b) a TEM image.
References
(1) J.-S. Rieh et al., "Performance and design considerations for high speed
SiGe HBTs of fT/fmax=375GHz/210GHz," Int. Conf. on InP and Related
Met., p. 374, 2003.
(2) J.-S. Rieh et al., " SiGe HBTs for milimeter-wave applications with simultaneously optimized fT and fmax of 300GHz," RFIC Symp., p. 395, 2004.
(3) J. Böck et al., "SiGe bipolar technology for automotive radar applications,"
in Proc. BCTM, p. 84, 2004.
(4) H. Rücker et al., "SiGe:C BiCMOS technology with 3.6 ps gate delay,"
IEDM Tech. Dig., p. 121, 2003.
(5) B. Jagannathan et al., "3.9 ps SiGe HBT ECL ring oscillator and transistor
design for minimum gate delay," IEEE Electron Device Lett., vol 24, pp.
324-326, May 2003.
(6) B. Heinemann et al., "A complementary BiCMOS technology with high
speed npn and pnp SiGe:C HBTs," IEDM Tech. Dig., p 117, 2003.
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10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
pnp
npn
VCB = 0V
T=300K
-1.0 -0.8 -0.6 -0.4
0.4 0.6 0.8 1.0
Base-Emitter Voltage (V)
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
Fig. 4. Gummel plots of separately fabricated npn and pnp SiGe:C HBTs
measured at VCB=0V with reference base doping (solid) and with
reduced base width (dashed). Drawn emitter area of two transistors in
2
parallel: AE=2 x (0.175 x 0.84)Pm . T=300K.
fT, fmax (GHz)
pnp
150
VCE=1.5V
400
fT
100
300
fT
250
fmax
2
'IB=10PA, T=300K
5
1
0
-3
T=300K
10
'V=300mV
pnp
5.9ps
AE=0.175x0.84Pm2
Ref. (4)
5
npn
100
50
0
10-4
10-3
10-2
Collector Current (A)
0
2
of two transistors in parallel: AE=2 x (0.175 x 0.84)Pm2. T=300K.
The same devices with 2 transistors in parallel were used for the
high frequency measurements shown in Fig. 6.
150
50
0
-1
0
0
1
Collector-Emitter Voltage (V)
-2
Fig. 5. Output characteristics of separately fabricated npn and pnp SiGe:C
HBTs in the high injection regime with reference base doping
(solid) and with reduced base width (dashed). Drawn emitter area
200
fmax
npn
10
npn
350
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pnp
W (ps)
AE=2x(0.175x0.84)Pm2
200
3
Collector Current (mA)
Base, Collector Current (A)
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2
AE=0.175x0.42Pm
10-4
10-3
10-2
Collector Current (A)
Fig. 6. Transit frequency fT and maximum oscillation frequency fmax vs.
collector current for transistors with reference base doping (solid) and
with reduced base width (dashed). Corresponding Gummel plots and
output characteristics are shown in Figs. 4, 5. Deembedded small-signal current gain h21 and unilateral gain U vs. frequency were used for
extrapolation of fT and fmax at 30GHz with -20dB per frequency
decade.
3.2ps
1
Current per Gate (mA)
10
Fig. 7. CML ring oscillator gate delay W vs. current per gate for oscillators
consisting of 53 stages with npn and pnp SiGe:C HBTs, respectively. T=300K, |VEE|=2.5V, differential voltage swing 300mV.
400
200
'V(mV)
350
fT, fmax (GHz)
5
npn
W (ps)
300
400
4
3.2ps
300
250
fmax
200
3
AE=0.175x0.84Pm2
150
1
Current per Gate (mA)
10
Fig. 8. CML ring oscillator gate delay W vs. current per gate at different voltage swings for oscillators with npn SiGe:C HBTs. T=300K,
VEE= ¯2.5V.
npn
fT
5
AE=2x(0.175x0.84)Pm2
15
25
35
Extrapolation Frequency (GHz)
45
Fig. 9. fT and fmax for two npn transistors extrapolated from various frequency points with -20dB per frequency decade. Corresponding fT
and fmax vs. IC curves extrapolated at 30GHz are shown in Fig. 6.
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Integration of High-Performance SiGe:C HBTs with Thin-Film SOI CMOS
H. Rücker, B. Heinemann, R. Barth, D. Bolze, J. Drews, O. Fursenko, T. Grabolla, U. Haak,
W. Höppner, D. Knoll, S. Marschmeyer, N. Mohapatra, H. H. Richter, P. Schley, D. Schmidt,
B. Tillack, G. Weidner, D. Wolansky, H.-E. Wulf, and Y. Yamamoto
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Abstract
A new scheme for the integration of high-performance
HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and
high-performance SiGe HBTs is solved by forming HBTs on
silicon islands in the BOX. Low-resistance collector wells are
realized by ion implantation into the SOI substrate. SiGe:C
HBTs with fT/fmax values of 220 GHz/230 GHz and a BVCEO
of 2.0 V and fully-depleted CMOS transistors with 90 nm
gate length are fabricated on SOI wafers with 30 nm Si thickness.
Introduction
SOI BiCMOS is a promising technology for mixed-signal
designs. The SOI substrate can be used to enhance the performance of FET devices and on-chip passive circuit components, and to minimize isolation problems. Scaled SOI [1]
and bulk [2] CMOS technologies with fT and fmax values in
the 200 GHz range can facilitate the implementation of an
increasing number of RF functions. However, highperformance HBTs remain indispensable for many mm-wave
applications and high bandwidth communication systems due
to their high voltage capability, high output resistance, low
1/f noise, and the large number of proven RF circuit concepts. Moreover, integration of SiGe HBTs can significantly
extend the accessible frequency range of RF CMOS technologies since SiGe HBTs continue to provide higher RF
performance than FETs of the same technology node.
The major challenge for SOI BiCMOS integration lies in
the different layer thicknesses needed for HBTs and CMOS.
The silicon thickness of about 1 Pm required for previously
demonstrated high-performance HBTs on SOI [3] is incompatible with advanced SOI CMOS. On the other hand, the
performance of HBTs on thin SOI is limited by an increased
collector resistance [4]. Here, we describe a new approach to
integrate high-performance SiGe HBTs on thin-SOI substrates. The process is compatible with fully-depleted SOI
CMOS without compromising HBT performance. The key
new process feature is the formation of low-resistive collectors in the silicon substrate below the buried oxide (BOX).
The HBTs are fabricated in windows of the BOX which are
filled by selective silicon epitaxy. This technology does not
use an epitaxially-buried subcollector or deep trench isolation
therefore facilitating an easy BiCMOS integration in a costeffective manner.
Device structure and fabrication
The devices were fabricated on UNIBOND SOI wafers
with 150 nm BOX and 30 nm Si thickness. The flow of the
BiCMOS process is shown schematically in Fig. 1. The HBT
SOI CMOS flow
x
x
x
x
x
Definition of active MOS areas
Gate oxide formation & poly deposition
Pre-doping of n+ and p+ gates
Gate structuring & dummy spacer formation
Selective growth of elevated S/D regions
x
x
x
x
x
x
x
S/D implantation
Wet etching of MOS dummy spacers
S/D extension and halo implantation
Spacer formation
Final RTA
Co salicidation
Metallization
HBT module
x
x
x
x
x
x
x
x
x
x
Deposit MOS protection layer
Window opening in BOX for HBTs
Selective Si epitaxy in BOX windows
Collector well and SIC implantation
HBT base epitaxy
Emitter window opening
Deposition & structuring of As doped Emitter
Formation of elevated extrinsic base regions
Base structuring
Wet etch MOS protection layer
Fig. 1: SOI BiCMOS flow
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Elevated S/D
Buried oxide
Substrate
Fig. 2: Cross section of a MOSFET after selective growth of elevated S/D
regions
(a)
(b)
Fig. 4: SEM cross section of FD SOI MOSFET with elevated S/D
regions and 90 nm gate length
Nitride
Inside spacer
Selective Si epitaxy
Collector well
Fig. 3: Schematic cross sections illustrating the fabrication of HBT collector
wells. (a) After dry etching BOX windows and inside spacer formation (b)
After selective epitaxy and collector well implantation. The two windows in
the BOX are used for the active HBT region and the collector contact.
module is fabricated after CMOS gate formation. For the
CMOS process, a replacement spacer concept was adopted
[5]. After structuring pre-doped poly-Si gates, dummy spacers are formed and elevated S/D regions are grown by selective epitaxy (Fig. 2). All MOSFET channel and S/D implants
are performed after the HBT module. Consequently, the
CMOS doping profiles are not affected by the HBT integration. The threshold voltages of the CMOS devices are adjusted by halo implants. Halos and S/D extensions are
implanted after HBT fabrication and after removing the
dummy spacers from the gates.
The HBT module starts with the formation of windows in
the BOX (Fig. 3). A sequence of dry etching, inside spacer
formation and wet etching of the BOX is used to form windows which widen towards the bottom of the BOX. The
windows are filled by selective Si epitaxy. The particular
shape of the window reduces the collector resistance and
Fig. 5: SEM cross section of an HBT on SOI substrate. The highly
conductive collector well is formed in the Si substrate below the buried
oxide.
ensures a facet-free Si surface in the active transistor area.
Next, the collector wells are implanted and selectivelyimplanted collector (SIC) pedestals are formed. During the
subsequent HBT process, CMOS regions are protected by an
oxide/nitride layer stack which is opened in active HBT regions. The HBT stack with the C-doped SiGe base is grown
by non-selective epitaxy. The fabrication of the emitter and
the self-aligned elevated extrinsic base regions is performed
as described in [6]. The back-end-of-line process with aluminium metallization was adopted from a 0.25 Pm BiCMOS
process [7]. Cross sections of the final MOS and HBT structures are shown in Figs. 4 and 5.
A major concern for SOI devices is self-heating. In the present concept, the thermal resistance of the HBTs is not increased by the use of SOI wafers. This is due to the absence
of the BOX below the active HBT regions. This is in contrast
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-1.2
300
VD=-0.05V
VD=0.05V
PMOS
-0.8
NMOS
-0.4
0.0
0.4
0.8
1.2
-3
10
-5
10
200
-7
10
-9
10
VCB=0V
100
T=300K
-11
10
AE=0.21 x 0.84 Pm
2
-13
10
Gate Voltage (V)
0.4
0.6
Current Gain
VD=1.2V
VD=-1.2V
Base, Collector Current (A)
Drain Current (A/Pm)
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
0.8
0
1.0
Base-Emitter Voltage (V)
Fig. 6: Transfer characteristics of NMOS and PMOS (Lgate=90nm) FD SOI
transistors.
PMOS
NMOS
400
VGS=1.2 V
300
1.0 V
200
100
0
-1.2
VGS=
-1.2 V
0.8 V
-1.0 V
-0.8 V
-0.6 V
0.6 V
-0.8
-0.4
0.0
0.4
0.8
5
Collector Current (mA)
Drain Current (PA/Pm)
500
IB(PA)
30
25
20
15
10
4
3
2
1
Fig. 7: Output characteristics of NMOS and PMOS (Lgate=90nm) FD SOI
transistors
to previous approaches to SiGe HBTs on SOI which showed
a significant increase of the thermal resistance due to the low
thermal conductance of the buried oxide [8].
Device Results
A. CMOS transistors
Measured transfer and output characteristics of fullydepleted NMOS and PMOS transistors with physical gate
length of 90 nm and a nitrided gate oxide with
Tox(acc) = 2.4 nm are shown in Figs. 6 and 7. At Vdd = 1.2 V,
NMOS transistors demonstrate an Ion = 460 PA/Pm and
Ioff = 5 nA/Pm and PMOS transistors show Ion = 210 PA/Pm
and Ioff = 0.4 nA/Pm. The threshold voltages of NMOS and
PMOS devices are 0.4 V. The sub-threshold swing at
VDS = 0.05 V is 85 and 80 mV/dec for NMOS and PMOS
devices, respectively.
AE = 0.21 x 0.84 Pm
2
5
BVCEO=2.0V
1.2
Drain Voltage (V)
100
Fig. 8: Gummel characteristics of an HBT with drawn emitter areas of
0.21 x 0.84 Pm2.
0
0.0
0.5
1.0
1.5
2.0
Collector-Emitter Voltage (V)
2.5
Fig. 9: HBT output characteristics at high injection.
B. HBT DC characteristics
The Gummel plot of an HBT on SOI with drawn emitter
area of 0.21 x 0.84 Pm2 is shown in Fig. 8. The devices have
a current gain of 250 at VBE=0.7 V and ideal Gummel characteristics over more than five decades of current. Common
emitter output characteristics at fixed base currents are plotted in Fig. 9 for high current injection, i.e, up to 1.5 times the
collector current density at peak fT. Due to the heat contact of
the devices to the substrate wafer there is only a weak indication of self-heating at high collector currents. The devices
have an open-base E-C breakdown voltage BVCEO = 2.0 V
and a B-C breakdown voltage BVCBO = 5.8 V. An Early voltage of 180 V was extracted from the output characteristics at
fixed VBE = 0.7 V (Fig. 10).
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200
1.0
0.5
VBE=0.7 V
2
AE=0.21 x 0.84Pm
0.0
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250
1.5
0
1
2
Collector-Emitter Voltage (V)
fT, fmax (GHz)
Collector Current (PA)
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VCE=1.5 V
150
100
fmax
fT
50
0
-5
10
AE=2 x (0.21 x 0.84)Pm
10
-4
10
-3
2
10
-2
Collector Current (A)
Fig. 10: Collector current vs. collector-emitter voltage at VBE=0.7V
Fig. 11: Transit frequency fT and maximum oscillation frequency fmax vs.
collector current.
C. HBT RF characteristics
The cutoff frequency fT and the maximum oscillation frequency fmax were extracted from s-parameter measurements
extrapolating at a frequency of 30 GHz with a -20 dB/decade
slope from Ňh21Ň and Mason’s unilateral gain U, respectively. Fig. 11 shows fT and fmax as a function of collector
current. A peak fT value of 220 GHz and a peak fmax value of
230 GHz are achieved.
The demonstrated fT values of the present SOI process exceed those of our previously reported 0.25 Pm BiCMOS
process on bulk Si wafers [6] by about 20 GHz. This improvement was achieved although the collector resistance of
the HBTs on SOI wafers (RC=36 : @ AE=0.21 x 0.84 Pm2)
is about twice as high as that of the reference HBTs on bulk
Si due to the different collector design. Main causes for the
increased speed of the present HBTs are: (1) a steeper base
doping profile due to the reduced final RTA for the 90 nm
SOI CMOS flow, and (2) an optimized collector profile facilitated by SIC implantation before base epitaxy.
Conclusions
In summary, we have demonstrated a new integration
scheme for high-performance SiGe HBTs on thin-film SOI.
The thickness incompatibility problem of SOI CMOS and
high-performance SiGe HBTs was solved by forming HBTs
on Si islands in the BOX using implanted collector wells
below the BOX. SiGe:C HBTs with fT/fmax values of
220 GHz/230 GHz and fully-depleted CMOS transistors with
90 nm gate length were integrated on thin-body SOI wafers.
This new scheme opens the way for BiCMOS technologies
combining state-of-the-art SOI CMOS and bipolar performance.
Acknowledgment
The authors thank the team of the IHP pilot line for excellent support
References
[1] N. Zamdmer et al., “A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI
CMOS SoC technology with low-power millimeter wave digital and RF
circuit capability”, VLSI Technology Symposium 2004, pp. 98-99.
[2] K. Kuhn et al., “A comparison of state-of-the-art NMOS and SiGe HBT
devices for analog/mixed-signal/RF circuit applications”, VLSI Technology Symposium 2004, pp.224-225.
[3] K. Washio et al., “A 0.2Pm 180-GHz-fmax 6.7-ps-ECL SOI/HSR selfaligned SEG SiGe HBT/CMOS technology for microwave and highspeed digital applications” IEEE TED vol. 49, p. 271, 2002.
[4] J. Cai et al., “Vertical SiGe-base bipolar transistor on CMOS-compatible
SOI-substrate”, BCTM 2003.
[5] H. v. Meer and K. De Meyer, “The spacer/replacer concept: A viable
route for sub-100 nm ultrathin-film fully-depleted SOI CMOS”, IEEE
EDL vol. 23, pp. 46-48, 2002.
[6] H. Rücker et al., “SiGe:C BiCMOS technology with 3.6 ps gate delay”,
IEDM 2003, pp. 121-124.
[7] D. Knoll et al., “BiCMOS integration of SiGe:C heterojunction bipolar
transistors”, BCTM 2002, pp. 162-166.
[8] M. Mastrapasqua et al., “Minimizing thermal resistance and collector-tosubstrate capacitance in SiGe BiCMOS on SOI”, IEEE EDL vol. 23, 145147, 2002.
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A modular, low-cost SiGe:C BiCMOS process
featuring high-fT and high-BVCEO transistors
Dieter Knoll, Bernd Heinemann, Rainer Barth, Katrin Blum, Johannes Borngräber,
Jürgen Drews, Karl-Ernst Ehwald, Gerhard Fischer, Alexander Fox, Thomas Grabolla,
Ulrich Haak, Wolfgang Höppner, Falk Korndörfer, Beate Kuck, Steffen Marschmeyer,
Harald Richter, Holger Rücker, Peter Schley, Detlef Schmidt, Rene Scholz,
Biswanath Senapati, Bernd Tillack, Wolfgang Winkler, Dirk Wolansky, Christoph Wolf,
Hans-Erich Wulf, Yuji Yamamoto, and Peter Zaumseil
IHP, Im Technologiepark 25, 15 236 Frankfurt (Oder), GERMANY
tel.: (+49) 335-5625-176, fax: (+49) 335-5625-327, e-mail: [email protected]
Abstract. We demonstrate a BiCMOS process
which uses only 22 mask steps to fabricate four
types of SiGe:C HBTs, in combination with a
triple-well, 2.5V CMOS core and a full menu of
passive elements. Key process feature is a 2-mask
HBT module. We show that transistors with peak
fT values ranging from 30GHz (@ 7V BVCEO) up to
130GHz (@ 2.1V BVCEO) can be fabricated with
this low-cost module. Among the passives are
varactors, polysilicon resistors, and a 2fF/µm2
MIM-capacitor. Five layers of Al are available,
including 2µm and 3µm thick upper layers. SOC
ability of the process is demonstrated by a 1MSRAM yield of typically 70%.
strong yield increase for VLSI segments. The process
now features a 1M-SRAM yield of typically 70%. (4)
The thickness of the MIM-cap nitride layer was
reduced to double the capacitance density. The new
capacitor combines 2fF/µm2 density with a second
order voltage coefficient of less than 10ppm/V2. (5) A
fifth, 3µm thick Al layer was added to the 2µm thick
upper metal level of the previous process to get higher
quality factors of BEOL-based passive elements.
Further process features are a MOS and a p+n
junction varactor with tuning ranges of 3.2:1 and
1.7:1, respectively, and several polysilicon resistors
with up to 2.3kΩ sheet resistance.
For fabricating the full device menu, the new
process uses only 22 mask steps.
I. INTRODUCTION
BiCMOS RF performance has strongly been
improved during the last years by the integration of
SiGe:C HBTs which reach meanwhile transit and
maximum oscillation frequencies (fT, fmax) in excess
of 200GHz [1-3]. For many applications, however,
cost plays the key role. Therefore, companies develop
not only high-end platforms, which are costly in the
most cases, but also release low-cost derivatives to
cover a wide spectrum of market segments [4, 5].
Here, we present a modular SiGe:C BiCMOS
platform, which compromises cost and performance
at a level not published so far. In comparison to IHP’s
previous low-cost process [5], the new one includes
some improvements which can be summarized as
follows: (1) The highest available HBT-fT was
increased from 80GHz to 130GHz, while the
collector-emitter breakdown voltage (BVCEO) lowered
from 2.4V to 2.1V only. This improvement was
achieved by adding a new chain of collector implants
to the 1-mask HBT module of the previous process,
and shrinking the HBT vertical dimensions. (2) HBTs
with up to 20µm emitter length can be fabricated with
same RF performance as sub-µm devices. This is an
important result for devices which do not use a
buried, highly-doped subcollector, and was achieved
by improved transistor layouts. (3) The flow for the
CMOS process core was modified resulting in a
102
STI (1), DEEP N IMP (2)
HP-HBT IMP (3)
NWELL IMP (4), PWELL IMP (5)
GATE STACK DEPOSITION
HBT MODULE (6)
GATE (7), SPACER, NSD IMP (8), PSD IMP (9)
SALBLOCK (10), Co SALICIDE, CONT (11)
MET1 (12), VIA1 (13), MIM (14)
MET2 (15), VIA2 (16), MET3 (17), VIA3 (18)
MET4 (19), VIA4 (20), MET5 (21), PAD (22)
Figure 1. Flow diagram of the BiCMOS process. The
numbers included illustrate the mask step sequence.
II. BiCMOS PROCESS FLOW
Fig. 1 shows a flow diagram of the complete
process. In comparison to the previous, 19-mask
BiCMOS process, we added 3 mask steps, the first
one for the fabrication of the new, high-fT HBT, and
the further ones for the integration of the 5th Al layer.
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“E”
of HBT1, HBT2, and HBT3 are formed identically to
the previous process. For the collector region of the
new, high-fT HBT4, we use an implant chain (masked
HP-HBT IMP, see Fig. 1) taken from our first high
performance BiCMOS generation [6, 7]. Compared to
the epi process applied previously, we reduced, by a
few nm, the widths of the Si layers grown before and
after SiGe:C base layer deposition, respectively.
“B”
p+ Gate
W
Poly
CoSi
STI
SiGe:C
Oxide Spacer n+ Emitter
Figure 2. SEM cross-section of a SiGe:C HBT,
fabricated with a CMP-based HBT module.
The particular transistor structure, shown in Fig. 2,
results from the application of the previously
described 1-mask HBT module which uses CMP for
separating the highly doped emitter from the external
base [5]. CMOS processing steps such as the gate RIE
and the PMOS S/D implantation (PSD) are
simultaneously used for structuring and doping the
HBT external base regions, respectively.
HBT1
EMITTER
SIC
NSD
COLLWELL
III. HBT PERFORMANCE
Fig. 4 shows fT and fmax as a function of the
collector current for HBT4s differing in the emitter
width. The transistors reach a peak fT value of
130GHz and fmax values up to 150GHz, at 2.1V
BVCEO (Fig. 5), and a current gain of about 300 (Fig.
6). DC and RF parameters of the higher-voltage
HBTs are summarized in Table 1. These transistors
show combinations of fT and BVCEO values ranging
from 30GHz/7V up to 90GHz/2.1V.
fT or fmax (GHz)
“C”
140 AE,eff= 10x (wE,eff x 0.82) µm2
120
w = 0.24µm
100 E,eff
fmax
80
wE,eff= 0.4µm
60
40
VCE= 1.5V
fT
20
NWELL
10
DEEP N IMP
HBT2
SIC
STI
COLLWELL
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NSD
-4
-3
10
10
Collector Current (A)
-2
Figure 4. Transit (fT) and max. oscillation frequency
(fmax) vs. collector current for HBT4s differing in the
effective emitter width (by extrapolating the 30GHz,
de-embedded h21 and U values, respectively).
NWELL
DEEP N IMP
Figure 3. Schematic cross-sections of the different
HBTs fabricated in the 22-mask BiCMOS process.
ParaValue
Unit
Remark
meter
HBTs
Beta
300
VBE= 0.7V
1-4
2.5
V
@ 1µA
BVEBO
GHz VCE= 2V
fT/fmax * 30/70
BVCEO
HBT1
>7
V
0.5mA
>20
V
@ 0.1µA
BVCBO
GHz VCE= 2V
fT/fmax * 50/100
BVCEO
HBT2
4
V
0.5mA
17
V
@ 0.1µA
BVCBO
fT/fmax * 90/90
GHz VCE= 1.5V
fT/fmax # 90/95
HBT3
2.1
V
0.5mA
BVCEO
7.7
V
@ 0.1µA
BVCBO
fT/fmax* 130/138
GHz VCE= 1.5V
fT/fmax # 130/150
HBT4
2.1
V
0.5mA
BVCEO
6.8
V
@ 0.1µA
BVCBO
# AE,eff= (0.24x0.82) µm2
* AE,eff= (0.4x0.82) µm2;
Fig. 3 shows cross-sections of the 4 types of HBTs
fabricated by the new process. The collector regions
Table 1. Parameters of the four types of HBTs
fabricated in the 22-mask BiCMOS process
Device
GATE=EXT. BASE
SIC
COLLWELL
HBT3
NSD
NWELL
DEEP N IMP
HBT4
SIC
NSD
COLLWELL
HP-HBT IMP
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103
Collector Current (A)
0.020
Reprints of
Selected Publications
AE,eff= 10x(0.24x0.82) µm
2
100
80
60
40
0.016
0.012
0.008
20
0.004
IB (µA) 0
0.000
0.0
0.5
1.0
1.5
2.0
Collector-Emitter Voltage (V)
2.5
Base or Collector Current (A)
-3
10
-5
10
-7
10
-9
10
IC
IB
VCB= 0V
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Base-Emitter Voltage (V)
Fig. 6. Gummel plot of an HBT4.
VCE= 2V
lE,eff
0.82µm
-5
20µm
fT
fT
10
fmax
fmax
-4
-3
10
10
Collector Current (A)
HBT2
HBT1
HBT4
70
60
0
5
10
15 20
Wafer ID
25
30
35
SRAMS measured on 45 wafer sites
BEC= 0
100
80
60
40 AB C D E F G H I
20
CMOS
0
20
40
Fig. 8 compares yield data of arrays with different
HBT types. Obviously, the yield of HBT4-arrays is
only slightly lower compared to that of the lower
doped devices demonstrating that the high collector
doping of HBT4 does not lead to serious defect
issues.
K
J
L
M
BiCMOS lots
60
80
100
120
14 0
16 0
1 80
2 00
220
240
Lot ID (A-M)
-2
10
Fig. 7. Transit (fT) and max. oscillation frequency
(fmax) vs. collector current for HBT1s differing in the
emitter length (effective emitter width is 0.4µm).
104
80
As test vehicle for the VLSI ability of the new
process we used a 1M-SRAM with a 6-transistor cell.
To study the impact of HBT integration on the yield
of this 6-million transistor device, lots were fabricated
with and without HBT module. Fig. 9 demonstrates a
typical SRAM yield of around 70% for both cases
showing that our HBT integration scheme is modular
and has no negative impact on the yield of dense
CMOS sections. Moreover, it shows that the new
BiCMOS process guarantees high yield for VLSI
CMOS segments necessary for a cost effective
fabrication of RF-SOC’s. Note that we considered an
SRAM to be a good device only in the case that it
showed a Bit Error Count (BEC) of zero for all of the
24 tests we applied in total (“solid 0”, “solid 1”, and
several “checkerboard” tests were carried out at four
different supply voltages ranging from 1.2V to 3.2V).
1M-SRAM Wafer Yield (%)
fT or fmax (GHz)
Fig. 7 demonstrates very similar RF performance
for HBTs with short and long emitter fingers. This is
an important result for a technology which does
without a costly module for fabricating an epitaxially
buried, highly-doped subcollector. It was achieved by
improved device layouts facilitating a good RB
scaling behavior without compromising RC.
80
70
60
50
40
30
20
10
0
90
IV. VLSI ABILITY OF THE PROCESS
2
AE,eff= 10x(0.24x0.82) µm
-11
ICEs (@VCB=2V) meas. on 45 wafer sites
100
Fig. 8. Wafer yield of 4k arrays with different types of
HBTs (AE,eff= 4096x(0.4x0.82) µm2).
Figure 5. HBT4 output characteristics.
10
Yield of 4k HBT-Arrays (%)
Nachdrucke
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Fig. 9. Yield trend chart for 1M-SRAMs fabricated in
a complete BiCMOS flow or a flow w/o HBT module.
The MOS parameters of the BiCMOS process are
summarized in Table 2.
V. PASSIVE ELEMENTS
The data of passive elements available in the
process are also summarized in Table 2. These
elements, such as the accumulation type MOS
varactor with wide tuning range or the 250Ω, lowTCR polysilicon resistor show state-of-the-art
properties. Predefined inductors with inductance
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values ranging from 1 to 15nH and quality factors
ranging from 6 (for a 15nH inductor @ 2.4GHz) to 16
(for a 1nH inductor @ 5.8GHz) can also be used.
NMOS/
Isolated
NMOS
PMOS
MOS
Varactor
Parameter
IDS
IOFF
VT
LEFF
IDS
IOFF
VT
LEFF
Tuning
range
Value
570
3
0.62
0.22
290
3
-0.51
0.185
Unit
Remark
µA/µm
VDS= 2.5V
pA/µm
V
µm
µA/µm
VDS= 2.5V
pA/µm
V
µm
Q
35/20
6
2800
250
-21
110
2300
-2500
2
<10
>17
1.7:1
Ωsq
ppm/°C
Ωsq
ppm/°C
ppm/°C
Ωsq
ppm/°C
fF/µm2
ppm/V2
V
p+ poly
(-30)-27°C
27-125°C
low-doped
poly
TTBD (sec)
Normalized Capacitance
1.0000
40
60
80
Frequency (GHz)
100
120
7
1pA/µm
T= 125°C
10
5
10
3
10
1
10
6
Fig. 11. S12 magnitude vs. frequency for a
transmission line.
8 10 12 14 16
Voltage (V)
In summary, we have demonstrated a new SiGe:C
BiCMOS process of exceptional simplicity, flexibility
and performance. It offers four different HBT types,
including a 130GHz-fT and a 7V-BVCEO transistor, by
adding only two mask levels to standard RF CMOS.
The combination of this two-mask HBT module with
a highly integrated digital CMOS backbone and
advanced passive elements meets the needs of the vast
majority of applications in a cost-effective way.
IX. REFERENCES
2
Fig. 10 shows the C(V) characteristics of the new,
2fF/µm2 MIM-cap, demonstrating a very low second
order voltage coefficient of less than 10ppm/V2. For
this MIM-cap, a much thinner nitride layer is used,
compared to the previous process. However, lifetime
(see insertion of Fig. 10) and breakdown voltage
(Table 2) are high enough for the targeted
applications of the BiCMOS process.
1.0001
20
VI. SUMMARY AND CONCLUSIONS
@5GHz for
low/high C
Table 2. MOS devices and passive elements of the 22mask BiCMOS process.
1.0002
T-Line Length: 5.05mm
T-Line Width: 12.2µm
0
@5GHz for
low/high C
75/25
Salicide RS
Resistor TCR
RS
Poly-Si
TCR(a)
Resistor
TCR(b)
Poly-Si RS
Resistor TCR
Unit C
MIM
VCC2
Cap
BV
1.0003
-1
-2
-3
-4
-5
-6
-7
3.2:1
Tuning
range
p+n
Varactor
Q
1.0004
One benefit we take from the fifth, thick metal
layer is demonstrated by the low losses of
transmission lines fabricated with this layer (Fig. 11).
S21 Magnitude (dB)
Device
Reprints of
Selected Publications
[1] B.A. Orner et al., “A 0.13µm BiCMOS technology
featuring a 200/280GHz (fT/fmax) SiGe HBT”, Proc. of the
2003 BCTM, pp. 203-206.
[2] H. Rücker et al., “SiGe:C BiCMOS technology with
3.6ps gate delay”, IEDM 2003 Tech Dig., pp. 121-124.
[3] T. Hashimoto et al., “Direction to improve SiGe
BiCMOS technology featuring 200-GHz HBT and 80nm
gate CMOS”, IEDM 2003 Tech. Dig., p. 129-132.
[4] N. Feilchenfeld et al., “High performance, low
complexity 0.18µm SiGe BiCMOS technology for wireless
circuit applications”, Proc. of the 2002 BCTM, p. 197-200.
[5] D. Knoll et al., “A flexible, low-cost, high performance
SiGe:C BiCMOS process with a one-mask HBT module”,
IEDM 2002 Tech. Dig., pp. 783-786.
[6] B. Heinemann et al., “Cost-effective high-performance
high-voltage SiGe:C HBTs with 100GHz fT and BVCEO x fT
products exceeding 220VGHz”, IEDM 2001 Tech. Dig., pp.
348-351.
[7] D. Knoll et al., “BiCMOS integration of SiGe:C
heterojunction bipolar transistors”, Proc. of the 2002
BCTM, pp. 162-166.
T= 27°C
2
VCC1= 34.4ppm/V VCC2= 8.3ppm/V
0.9999
-6
-4
-2
0
2
4
6
Voltage (V)
Fig. 10. C(V) characteristics of the 2fF/µm2 MIMcapacitor (A= (202x102) µm2). Inserted is a lifetime
extrapolation curve.
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
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Reprints of
Selected Publications
A Two Mask Complementary LDMOS Module
Integrated in a 0.25 µm SiGe:C BiCMOS Platform
K.E. Ehwald, A. Fischer, F. Fuernhammer, W. Winkler, B. Senapati, R. Barth, D. Bolze,
B. Heinemann, D. Knoll, H. Ruecker, D. Schmidt, I. Shevchenko, R. Sorge, H.-E. Wulf
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany,
Tel: +49 335 /5625 780, Fax: +49 335/ 5625 327, Email: [email protected]
Abstract:
The integration of RF n-and p-LDMOS transistors into a
CMOS or BiCMOS platform allows the use of
complementary circuit techniques and enables efficient
solutions for linear RF power amplifiers, power
switches, DC/DC converters and high voltage IO
circuits. We demonstrate the modular integration of high
performance n-LDMOS devices and a record p-LDMOS
transistor into a low-cost 0.25µm SiGeC RF-BiCMOS
technology. In addition to n-LDMOS transistors on psubstrate with breakdown voltages near 30V, isolated nLDMOS- and p-LDMOS transistors can be
manufactured on the same wafer and achieve
breakdown voltages of 11.5V and 13.5V and fT/fmax
values of 23/48 GHz or 13/30 GHz, respectively.
1.
Introduction
RF LDMOS transistors are promising candidates to
realize integrated power amplifiers for wireless
applications and other high-speed, high-voltage circuits,
e.g. for IO ports. Integration of n-LDMOS devices in RF
BiCMOS technologies has been demonstrated previously
[1,2]. In this paper we demonstrate the additional
integration of p-LDMOS transistors into a low cost
0.25µm BiCMOS process to enable the application of
complementary circuit techniques. The approach
described in [1] for the n-LDMOS integration into a
0.25µm BiCMOS process, was applied in this work
analogously to integrate the p-LDMOS devices. In
addition to the new p-LDMOS and to the n-LDMOS
devices described in [1], a new high performance
n-LDMOS transistor, isolated from the p-substrate by a
high energy implanted n-buried layer, was also realized.
This way, n- and p-LDMOS transistors both isolated
from the p-substrate can be manufactured at the same
wafer. The underlying RF SiGe:C BiCMOS process with
only 19 mask steps was published in [3]. It offers 2.5V nand p-MOS standard transistors, an isolated n-MOS
transistor, three kinds of npn HBT’s, three poly resistors,
MIM capacitors and four metal layers with a thick top
metal enabling high Q inductors. The implementation of
the new complementary LDMOS module into this
SiGe:C BiCMOS platform is an excellent base to realize
cost-effective, highly-integrated digital radio transceiver
106
architectures at microwave frequencies as well as
integrated fast power switches, high voltage I/O’s and
other internal high voltage circuits, e.g. for embedded
flash memories.
2.
Technology and Device Construction
The integration scheme for the n- and p-LDMOS
transistors is shown in Fig. 1. As for the n-LDMOS, also
for the p-LDMOS the thin gate oxide (5nm), the gate
polysilicon, the highly doped S/D-regions and the
correspondent well implants of the standard MOS
transistors are used together with a special LDD doping
profile in the drift region, which enables its full depletion
already at medium drain voltages, and a high breakdown
voltage. The salicide blocker mask, necessary for the
poly resistors, prevents the silicide formation in the drift
region between the highly doped drain and the gate.
Using this scheme, four preferred types of LDMOS
constructions (n-LDMOS1, n-LDMOS2, n-LDMOS3
and p-LDMOS) can be realized on the same wafer. The
position of the well- and LDD implants in these
constructions is visible from schematic cross sections in
Figs. 2a-2d. To ensure optimum connection to the gate
inversion layer, the masked LDD implantations n-LDD1
and p-LDD for n-and p-LDMOS are carried out
immediately after structuring the poly gates before
forming the gate spacers. A blanket n-LDD2
implantation (P and shallow BF2 [1] ) is employed after
the high dose S/D implants, but before S/D-RTA. Fig. 2a
shows the n-LDMOS1 device as described in [1]. This
device construction is applicable up to drain voltages of
about 30V. The drift region outside of the p-well is
doped by the n-LDD2 implantation only, resulting in a
doping profile with a reduced net concentration in this
area. The masked n-LDD1 implant is restricted to a small
part of the drift region near the gate, but overlaps the
poly gate and the p-well. A simplification of this layout
is possible, if a BVDS value of about 16-17 V is
sufficient, corresponding to a (drawn) drift length ≤
0.8µm. In this case the n-LDD1 implantation mask can
be open in the whole drift and gate region, without
degrading the static or dynamic electrical parameters, but
reducing the sensitivity to mask misalignment. Figs. 2b
and 2c show the n-LDMOS2 and n-LDMOS3 device
constructions with substrate connected and with isolated
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p-well, respectively, both with the n-LDD1 being
implanted in the complete drift region.
Fig. 2d shows the cross section of the p-LDMOS
device. Here, similar as for n-LDMOS2, the well
implantations are masked in the drain area and in the
drift region near the drain and the mask window for the
p-LDD implantation is open completely in the active
area of the transistor.
Note, that the integration of the four LDMOS
transistor constructions on the same wafer requires only
2 additional masks on top of the SiGe:C BiCMOS flow,
resulting in a total number of only 21 mask steps for the
complete process.
3.
Reprints of
Selected Publications
Figs. 6 and 7 show for the p-LDMOS transistor the
results of S-parameter measurements, using an HP 8510
network analyzer. At VDS= 8V, fT values up to 13.5 GHz
and fmax values up to 32 GHz were measured. These are,
according to our knowledge, the highest cutoff
frequencies for p-LDMOS transistors published up to
now. DC and RF modeling of the different LDMOS
transistors was carried out using BSIM3V3 with adapted
sub-circuits. The excellent fitting of RF and DC
measurement data is shown for the p-LDMOS in Figs. 5a
and 6 and for the isolated n-LDMOS transistor in Figs. 8
and 9. Based on these models complementary power
amplifiers and DC/DC converters, taking advantage of
the modular LDMOS technology module described here,
are currently in development .
Electrical Results and Discussion
Typical electrical results of the four LDMOS
constructions for different drift lengths are summarized
in Table 1. The parameters of the n-LDMOS1 transistors
for drift lengths of 1.0 and 0.6 µm are very similar to
those of the corresponding devices described in [1],
showing that the modified process flow has no
significant impact on the electrical parameters of the nLDMOS devices. Also, the throughout n-LDD1
implantation, applied to the 0.6µm n-LDMOS2 device,
causes no essential drawbacks with respect to its static or
dynamic parameters. This shows, that for this drift length
the electrical field distribution in the drift region at a
voltage close to breakdown is not changed significantly
by a higher net doping in the very small LDD region “A”
between the p-well edge and the n+ drain (Fig. 2b). This
is in contrast to the results obtained for a drift length of
1.4µm with a much larger LDD region ”A”, where the
breakdown voltage is drastically reduced from 29V to
about 18V, if the n-LDD1 doping was implanted in the
complete active transistor region (compare n-LDMOS1
and n-LDMOS2 with LDrift = 1.4µm in Fig. 3).
The isolated n-LDMOS3 transistor shows RF
characteristics very similar to n-LDMOS1 and
n-LDMOS2, reaching fT/fmax of 24GHz/48GHz
respectively (Table 1). However, BVDS is limited by the
n+-drain to p-well breakdown to about 11.5V. So, BVDS
for nLDMOD3 is nearly independent from the driftlength in the range between 0.8µm and 0.4µm, as shown
in Fig. 4.
DC characteristics of the p-LDMOS device are
shown in Figs. 5a–5c. A BVDS value of 13.5V combined
with a RON of 11.5 Ωmm was obtained (Table 1). Similar
to the isolated n-LDMOS3, BVDS does not rise if the drift
length is increased above 0.6µm. It is limited then by the
vertical breakdown between the p+-drain and the highenergy implanted buried layer. The relatively low RON
value of the p-LDMOS results from the fact, that in
contrast to the n-LDD1 and n-LDD2 implantations of the
n-LDMOS devices, calculated for breakdown voltages
up to 30V, the p-LDD implantation could be optimized
for a relatively low breakdown voltage and a fixed low
drift length.
4.
Summary and Conclusions
Complementary high performance RF LDMOS
transistors with isolated wells were integrated into a lowcost 0.25µm SiGe:C RF-BiCMOS platform, using two
additional masks. The n- and p-LDMOS devices are
characterized and modeled. BVDS of 11.5V and -13.5V
as well as fT/fmax values of 23/48 GHz and 13.5/32 GHz
were demonstrated for isolated n-LDMOS and pLDMOS, respectively, in addition to n-LDMOS
transistors with p-well connected to p-substrate, offering
breakdown voltages up to 30V. The described approach
to integrate complementary RF LDMOS transistors can
be extended to 0.18µm and 0.13µm CMOS and
BiCMOS technology generations. This enables costeffective solutions for power devices in future “systemon-a-chip” wireless and broadband applications such as
handset-power amplifiers, integrated laser drivers, power
switches and high voltage circuits for I/O interfaces and
Flash programming.
References
[1] K.-E. Ehwald, B. Heinemann, W. Roepke, W.
Winkler, H. Rücker, F. Fuernhammer, D. Knoll, R.
Barth, B. Hunger, H.E. Wulf, R. Pazirandeh, and N.
Ilkov, “High Performance RF LDMOS Transistors with
5nm Gate Oxide in a 0.25µm SiGe:C BiCMOS
Technology", IEDM Tech Dig., pp. 895 (2001)
[2] B. Szelag, H. Baudry, D. Muller, A. Giry, D.
Lenoble, B. Reynard, D. Pache, A. Monroy, “Integration
and Optimization of a high performance RF Lateral
DMOS in an advanced BiCMOS Technology”,
ESSDERC 2003, Proceedings of the 33nd European
Solid-State Device Research Conference
[3] D. Knoll, K.-E. Ehwald, B. Heinemann, A. Fox, K.
Blum, H. Rücker, F. Fürnhammer, B. Senapati, R. Barth,
U. Haak, W. Höppner, J. Drews, R. Kurps, S.
Marschmeyer, H.H. Richter, T. Grabolla, B. Kuck, O.
Fursenko, P. Schley, B. Tillack, Y. Yamamoto, K.
Köpke, H.-E. Wulf, D. Wolansky and W. Winkler,
“A Flexible, Low-Cost, High Performance SiGe:C
BiCMOS Process with a One-Mask HBT Module”,
IEDM Tech Dig., pp. 775 (2002)
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SHALLOW
TRENCH
Reprints of
Selected Publications
n S/D
+
p S/D
DEEP
n-WELL
GATE
PATTERNING
n -LDMOS
(maskless)
p-WELL
n-WELL
n/p -LDMOS
(masked)
RESISTOR
SALICIDE
GATE OX &
POLY DEP.
GATE
SPACER
4LM, MIM
BACK-END
G
S
+
BIPOLAR
MODULE
D
p-LDD + n-LDD2
n+ p+
p+
n-well
n-buried layer
p- substrate
G
S
n-LDD1 n-LDD2
+n-LDD2 (P+BF2)
D
p+ n+
Fig. 2d: Schematic cross-section of the p-LDMOS
device.
n+
p-well
-
0.6µm
0.4µm
-12
10
1.4µm
-13
1.4µm
LDRIFT=0.8µm
-14
10
0
STI
Fig. 2a: n-LDMOS1 device as described in [1]
G
S
10
10
silicide
p-substrate
10
ID (A/µm)
p-well
-12
-13
VG= 0
10
2
4
6
8
VDS [V]
10 12
0
G
D
n-LDD1+ n-LDD2
- 0.75 V
-50
-100
+
+
n
n
p-well
n-buried layer
p-substrate
Fig. 2c: Substrate isolated n-LDMOS3 device with
blanket n-LDD1 and n-LDD2 implantations.
108
0
Fig. 4: Breakdown characteristics of the isolated nLDMOS3 transistor for different drift lengths.
ID(µA/µm)
S
30
-14
Fig. 2b: n-LDMOS2 device with blanket n-LDD1 and
n-LDD2 implantations.
B
10
10
region “A”
p-substrate
20
LDRIFT=0.6µm
LDRIFT=0.4µm
LDRIFT=0.8µm
-11
10
n-LDD1 + n-LDD2
n+
VDS (V)
VG= 0
Fig. 3: Breakdown characteristics of transistors nLDMOS1 and n-LDMOS2 for different drift lengths
D
p+ n+
n-LDMOS1:
Masked
LDMOS
implant
n-LDMOS2:
Maskless
LDMOS
implant
-11
ID (A/µm)
Fig. 1: Integration of n- and p-LDMOS devices into the
RF-BiCMOS process flow.
-150
-200
-1V
- 1.25 V
- 1.5 V
- 1.75 V
-2V
- 2.25 V
-250
VGS = - 2.5 V
-12 -10 -8 -6 -4
VDS(V)
Measured
Simulated
-2
0
Fig. 5a: Output characteristics of the p-LDMOS device.
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10
-7
10
-9
V DS = -0.1V
-11
0.5
10
-10V
(dB)
-5
0.5
10
h21, U , Gmax
-ID (A/µm)
Nachdrucke
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10
-13
10
-15
-2
-1
20
15
10
5
0
-5
0
U
h 21
9
10
10
Frequency (H z)
10
10
-13
10
-15
V G= 0
11
V GS
M eas.
Sim .
300
2.0 V
200
1.5 V
100
1.0 V
-12
-8
-4
V DS [V]
0
0
Fig. 5c: Breakdown characteristic of the p-LDMOS
device.
40
Measuerd
VDS = - 8V
10
10
fM E A S = 1 0 G H z
V DS= 8 V
0 .5
-0.5
1 .5
V G S (V )
M eas.
S im u l.
2 .0
2 .5
This
This
[1]
This
[1]
work
work
work
LDrift
µm
1.4
1.0
0.6
V
29
26
26
16
15
BVDS
ID, SAT
µA/µm
150
150
125
150
125
ILeakage
pA/µm <1.5
<1.5
<1.5
9
7.8
7
6.2
RON
Ωmm
12.9
fT,max (4V)
GHz
15
21
19
23
23
fT,max (8V)
GHz
14
GHz
14
19
17
30
30
fT,max (12V)
fmax, max (4V)
GHz
31
46
40
53
43
fmax,max (8V)
GHz
33
GHz
34
43
43
55
52
fmax,max (12V)
Table 1: LDMOS parameters (W/L=56µm/0.24µm, typical values)
p-LDMOS
Fig. 9: Measured and simulated fT and fmax vs. VGS
characteristics of the isolated n-LDMOS3 device.
n-LDMOS 1
n-LDMOS 1
n-LDMOS 1
1 .0
n-LDMOS 3
-1.5
-1.0
VGS(V)
Fig. 6: Measured and simulated fT and fmax vs. VGS
characteristics of the p-LDMOS device.
Unit
fT
n-LDMOS 2
-2.0
fm ax
fT
VDS = - 4V
8
V DS (V)
100
fmax
20
Parameter
4
Simulated
30
0
-2.5
0
Fig. 8: Measured and simulated output characteristics of
the isolated n-LDMOS3 device.
fT, fmax (GHz)
fT , fmax (GHz)
10
Fig. 7: Current gain and power gains vs. frequency of
the p-LDMOS device.
-9
-11
0.5
V DS= 8 V
V G S = 2 .4 V
10
ID (µA/µm)
-ID (A/µm)
10
0.5
G m ax
V G (V)
Fig. 5b: Subthreshold characteristics of the p-LDMOS
device.
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This
work
0.6
16
150
<1.5
6
22
20
This
work
0.6
11.5
150
<1.5
8
23
21
This
work
0.6
-13.5
-90
<1.5
11.5
11.3
13
53
54
48
48
22
30
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Remarks
@ 10pA/µm
@IVGI= 1.5V,VD= 5V
@VDS=BVDS -2V
@ VG= 2.5V
Extrapolated from
20GHz h21 values
Extrapolated from
20GHz U values
109
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APPLIED PHYSICS LETTERS
VOLUME 85, NUMBER 7
16 AUGUST 2004
Structure and thickness-dependent lattice parameters of ultrathin epitaxial
Pr2O3 films on Si(001)
T. Schroeder, T.-L. Lee, and J. Zegenhagena)
European Synchrotron Radiation Facility, 6, Rue Jules Horowitz, 38043 Grenoble, France
C. Wenger, P. Zaumseil, and H.-J. Müssig
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
(Received 10 March 2004; accepted 19 May 2004)
Pr2O3 grown heteroepitaxially on Si(001) is a promising candidate for applications as a high-k
dielectric in future silicon-based microelectronics devices. The technologically important thickness
range from 1 to 10 nm has been investigated by synchrotron radiation-grazing incidence x-ray
diffraction. The oxide film grows as cubic Pr2O3 phase with its (101) plane on the Si(001) substrate
in form of two orthogonal rotation domains. Monitoring the evolution of the oxide unit-cell lattice
parameters as a function of film thickness from 1 to 10 nm, the transition from almost perfect
pseudomorphism to bulk values is detected. © 2004 American Institute of Physics.
[DOI: 10.1063/1.1771465]
1(a) shows a specular ␪ – 2␪ measurement on a 4 nm thick
Pr2O3 film on Si(001) which provides this information by
revealing all oxide and substrate reflections situated on the
共00L兲 crystal truncation rod (CTR). Aside from the substrate
peaks, the observed oxide reflection suggests that (a) the oxide consists of only one phase and (b) this phase grows with
a single orientation on Si(001). Comparing the experimentally determined d spacing of this oxide reflection 共d
= 0.198 nm兲 with those of the different Pr2O3 phases known
from literature7 allows us to assign this peak to the (404)
reflection of the cubic Pr2O3 phase (space group: Ia3). This
result is found for all ultrathin Pr2O3 films studied in this
work except for the 1 nm thick Pr2O3 film. In the latter case,
the limited oxide thickness did not result in any detectable
oxide peak on the 共00L兲 CTR. Our study corroborates the
results of ␪ – 2␪ scans performed with laboratory x-ray
sources on thicker Pr2O3 layers 共⬎15 nm兲 on Si(001).4,6
The second question of interest is the azimuthal orientation of the oxide layer on the Si(001) surface. The answer is
given by the hk in-plane scan 共ᐉ = 0.1兲 along the bulk
In microelectronics, the good microprocessing capability, the high dielectric breakdown strength, and the quality of
the thermally and electrically stable Si– SiO2 interface made
SiO2 films the gate dielectric of choice over the last 40
years.1 However, for generations of ultralarge-scale integration circuits, the SiO2 gate must be replaced by an alternative
high-k dielectric and many candidates are studied.2 Among
these, thin epitaxial praseodymium sesquioxide 共Pr2O3兲 films
on Si(001) substrates show outstanding dielectric properties
for use as gate insulators.3,4 To optimize the performance of
this materials system, we studied the structural aspects of the
dielectric layer to correlate them with the electric properties
of devices with a Pr2O3 gate. In this letter, we report a synchrotron radiation-grazing incidence x-ray diffraction (SRGIXRD) study on the morphological properties of the heteroepitaxial system Pr2O3 / Si共001兲 for oxide film thicknesses
of technological importance 共1 to 10 nm兲.
The boron-doped Si(001) substrates were cleaned by a
standard procedure and an HF dip removed the native oxide
layer immediately before the wafers were loaded into the
ultrahigh vacuum chamber. The Pr2O3 layers were grown by
molecular-beam epitaxy, as reported elsewhere.5 Before exposure to air, the hygroscopic Pr2O3 films were protected by
an amorphous Si capping layer of several nm thickness.6 The
Pr–oxide layer thickness was determined by ex situ x-ray
reflectivity and quantitative fluorescence measurements of
the Pr L lines. Samples of 1, 2, 4, 6, and 10 nm thick Pr2O3
films were studied ex situ by SR-GIXRD at the insertion
device beamline ID 32 of the European Synchrotron Radiation Facility using a beam energy of 11 keV 共0.1127 nm兲.
For grazing incidence diffraction studies, a Kappa-six-circle
diffractometer was used with the incident angle of the beam
on the sample surface fixed to 0.3°. Substrate and oxide reflections are indexed with respect to their bulk lattices, intensities are given in counts per second.
The first question to answer is the vertical stacking of
the ultrathin Pr2O3 epilayer on the Si(001) substrate. Figure
Si 关11̄0兴 direction in Fig. 1(a) recorded for a 4 nm Pr2O3
layer on Si(001). This scan is representative of all samples
studied. Since the Si peaks are very sharp [full width at half
maximum (FWHM) of 0.002°], the broad oxide reflections
(FWHM of 3°) can be easily distinguished. Two oxide reflections are observed and can be assigned to the Pr2O3共040兲 and
to the Pr2O3共404̄兲 in-plane reflections.
This reciprocal space information gathered in Fig. 1(a)
determines the real space orientation of the Pr2O3 layer on
the Si(001) surface. As the Si(001) surface unit cell is rotated
around the Si(001) surface normal by 45° with respect to the
bulk lattice unit cell, the Si(001) surface unit-cell vectors a1
and a2 point along the 具110典 bulk Si direction.8 The clean
Si(001) surface is characterized by a 共2 ⫻ 1兲 reconstruction
and Si terraces separated by a monatomic step height separate two 共2 ⫻ 1兲 domains which are rotated by 90° with respect to each other.8 This is sketched in Fig. 1(a). It depicts
the orientation of the two 共2 ⫻ 1兲 Si rotation domains [ter-
a)
Author to whom correspondence should be addressed; electronic mail:
[email protected]
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110
races (1) and (2)] with respect to the bulk 关11̄0兴 direction.
1229
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FIG. 1. (a) Specular ␪ – 2␪ scan (top) and in-plane hk scan 共ᐉ = 0.1兲 along
Si关11̄0兴 (middle) of a 4 nm Pr2O3 film on Si(001). Bottom: 90° rotation
domain structure of the 共2 ⫻ 1兲 Si(001) surface (gray dots: Second layer Si
monomers; gray dots connected by black lines: First layer Si dimers). (b) hkl
mesh scans 共ᐉ = 0.1兲 around the Si共22̄0兲 peak of the Pr2O3 共404̄兲 reflections
(coordinate system: Oxide unit-cell orientation).
Scanning tunneling microscopy studies have shown the initial Pr2O3 growth on the 共2 ⫻ 1兲 reconstructed Si(001)
surface.5 The specular ␪ – 2␪ scan of Fig. 1 proves that the
cubic Pr2O3 grows with its rectangular (101) plane on the Si
surface. The highest number of coincidence lattice points
between the oxide and the semiconductor results when the
oxide in-plane unit-cell vectors b1 = 关101̄兴 and b2 = 关010兴 are
aligned along the in-plane Si(001) surface unit-cell directions
a1 and a2. The dimensions of the latter are given in case of
the 共2 ⫻ 1兲 reconstruction by 兩ar1兩 = 0.768 nm and 兩ar2兩
= 0.384 nm so that the substrate spacings 2 · 兩ar1兩 and 3 · 兩ar2兩
match the oxide unit-cell dimensions 兩b1兩 = 1.5771 nm and
兩b2兩 = 1.1152 nm within 3% respectively. The azimuthal orientation of the oxide layer unit cells on the 共2 ⫻ 1兲 reconstructed terraces (1) and (2) is shown in Fig. 1(a) by the
dashed rectangles denoted domains (1) and (2). Accordingly,
the existence of the two orthogonal oxide domains (1) and
(2) on the Si(001) surface causes in the in-plane hk scan of
Fig. 1(a) along the bulk Si 关11̄0兴 direction the presence
of the Pr2O3共404̄兲 and Pr2O3共040兲 in-plane reflections,
respectively.
As strain relaxation and associated defects due to the
lattice mismatch between oxide and Si might compromise
the Pr2O3 gate performance, the change in the lattice param-
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eters of the oxide as a function of film thickness must be
accurately known.
The azimuthal lattice parameter 兩b1兩 along the oxide
关101̄兴 direction was determined for all samples with the help
of the Pr2O3共404̄兲 reflection. The Pr2O3共404̄兲 diffraction
peaks were studied by hkl mesh scans 共ᐉ = 0.1兲 around the
Si共22̄0兲 substrate peak shown in Fig. 1(b). The very sharp
Si共22̄0兲 peak is situated in the center appearing as a single
point. In contrast, the Pr2O3共404̄兲 reflection exhibits a broad
shape. The oxide peak is centered around the Si共22̄0兲 substrate peak for films of 1 and 2 nm thickness but the oxide
reflection moves along the hk̄ diagonal toward smaller reciprocal space values when the film thickness is increased to 4,
6, and 10 nm. The variation of 兩b1兩 was extracted and the
result is plotted in Fig. 2(b). The bulk oxide unit-cell value
兩b1兩 of 1.577 nm is indicated by the dotted line and is 2.6%
bigger than the Si(001) substrate spacing of 2 · 兩ar1兩
= 1.536 nm (dashed–dotted line). This lattice misfit
共兩b1兩 ⬎ 2 · 兩ar1兩兲 compresses the oxide film along its 关101̄兴 direction. Films of 1 and 2 nm thickness exhibit pseudomorphic growth behavior but 兩b1兩 relaxes in thicker films toward
the oxide bulk value reached at 10 nm film thickness. Note
that the intensity of the oxide spots of the thicker films (4, 6,
and 10 nm) is asymmetric toward the Si共22̄0兲 reflection indicating that the compressed 共101̄兲 oxide lattice planes in the
vicinity of the Si substrate are also present in thicker films
pointing toward a gradual relaxation of strain.
In addition, the hkl mesh scans allow one to extract the
domain sizes of the oxide layer along the oxide [010] and the
关101̄兴 directions by determining the FWHM values along the
respective directions.9 The result is plotted in Fig. 2(b). As
the Pr2O3共404̄兲 oxide reflection exhibits for all film thicknesses an anisotropic spot shape, i.e., the spots are elongated
along the oxide [010] direction, a bigger domain size is always found along the 关101̄兴 direction. The better evolved
long-range order of the oxide along the latter direction is due
to the smaller lattice mismatch between substrate and epilayer along this azimuth, as pointed out in the following.
The azimuthal lattice parameter 兩b2兩 along the oxide
[010] direction was monitored by studying the Pr2O3共040兲
reflections. Figure 2(a) summarizes the in-plane hk scans at
l = 0.1 of the Pr2O3共040兲 diffraction peaks performed for 1, 2,
4, 6, and 10 nm thick Pr2O3 layers on Si(001). A strong shift
of the position of this oxide reflection along the hk̄ diagonal
toward bigger reciprocal space values is detected when the
film thickness is doubled from 1 to 2 nm [bottom panel in
Fig. 2(a)]. This shift continues for the 4 nm film but saturates
for the 6 and 10 nm thick films [top panel in Fig. 2(a)]. The
Pr2O3共040兲 diffraction peaks of the thicker films show a
shoulder structure toward lower reciprocal values indicated
by the arrow. Again, this demonstrates that strained (010)
oxide planes are present in the thicker films (4, 6, and
10 nm) toward the Si substrate. The main positions of the
various Pr2O3共040兲 reflections were used to extract the value
of 兩b2兩 plotted in Fig. 2(b). The bulk oxide unit-cell length
兩b2兩 of 1.115 nm along the [010] direction (dotted lines) is
smaller by 3.3% than the substrate-induced value of 3 · 兩ar1兩
= 1.152 nm (dashed–dotted line). This lattice misfit
共兩b2兩 ⬍ 3 · 兩ar1兩兲 extends the oxide film along its [010] direc-
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1231
tion peaks reasonably scales with the oxide thickness for 4,
6, and 10 nm thick layers, but a strong decrease in intensity
is occurring for the 1 and 2 nm thick Pr2O3 layer. In contrast
to the 1 nm film, the position of the Pr2O3共040兲 reflection of
the 2 nm thick oxide points to a more bulklike lattice constant. Figure 2(b) shows that the value 兩b2兩 = 1.129 nm is already close to the bulk Pr–oxide unit-cell length of
1.115 nm. The bulk value of 兩b2兩 is adopted for all oxide
films from 4 nm thickness.
Figure 2(b) shows the vertical unit-cell length 兩b3兩 along
the oxide [010] direction for the various film thicknesses
studied. These values were deduced from Pr2O3共404兲 reflections in specular ␪ – 2␪ scans which were detectable for all
films thicker than 1 nm. The 2 and 4 nm thick films show a
兩b3兩 value of 0.84 nm which reduces to 0.816 and 0.81 nm
for the 6 and 10 nm thick oxide layer, respectively. All these
(101) layer spacings are bigger than the oxide bulk value of
0.788 nm (dotted line). The presence of a 共Pr2O3兲y共SiO2兲x
phase may explain these results. X-ray diffraction (XRD)
studies on unprotected Pr2O3 layers 共⬎15 nm兲 show after
exposure to air in the specular ␪ – 2␪ scans a peak at slightly
smaller angles than the Pr2O3共404兲 reflection, indicating an
increase of the Pr2O3共101兲 lattice spacing to a value of
0.832 nm.6 Transmission electron microscopy (TEM) studies
suggest as a possible origin of this peak an enhanced silicate
formation due to oxygen diffusion to the Si substrate.6 As the
(101) layer spacing of 0.84 nm derived in this work is close
to this reported value, further evidence is given for the strong
influence of an interfacial silicate layer on the properties of
Pr2O3 films thinner than 4 nm. It is noted that the increased
value of 兩b3兩 (with respect to the bulk) in case of the 6 and
10 nm thick film is due to the fact that specular ␪ – 2␪ scans
probe the whole oxide layer thickness.
In conclusion, we determined the structure and orientation of the Pr2O3 epilayer on the Si(001) surface and monitored quantitatively the thickness dependence of the film lattice parameters over the technologically important thickness
range 共1 to 10 nm兲. The interface structure between oxide
and Si(001) substrate deviates from the oxide bulk structure,
possibly due to silicate formation. As the oxide/ Si interface
is of utmost importance for the performance of microelectronics devices, further studies are underway to disclose its
detailed structure.
FIG. 2. (a) hk in-plane scans 共ᐉ = 0.1兲 of the Pr2O3 共040兲 reflections of
different oxide film thicknesses. (b) Oxide unit-cell lattice parameters (top)
and domain sizes (bottom) as a function of thickness.
tion. Surprisingly, instead of a pseudomorphic growth, the
1 nm thick oxide film shows an unit-cell length 兩b2兩 of
1.168 nm which is bigger than the substrate-induced value of
1.152 nm. A possible explanation could be the formation of a
silicate at the oxide/ Si interface. Photoemission studies suggest the growth of such a 共Pr2O3兲y共SiO2兲x interface layer of
about 2 nm thickness.10 As such an interface reaction at the
oxide/ Si affects the structure factors of the Pr2O3 layer, further support for the presence of an interfacial phase is given
by an analysis of the Pr2O3共040兲 diffraction intensities.
Figure 2 shows that the intensity of the Pr2O3共040兲 diffrac-
112
1
T. Hori, Gate Dielectrics and MOS ULSIs, Springer Series in Electronics
and Physics Vol. 34 (Springer, Berlin, 1996).
2
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243
(2001).
3
H.-J. Müssig, H. J. Osten, E. Bugiel, J. Dabrowski, A. Fissel, and T.
Gumminskaja, IEEE International Integrated Reliability Workshop, Final
Report (IEEE, New York, 2001), p. 1.
4
H. J. Osten, E. Bugiel, and A. Fissel, Solid-State Electron. 47, 2161
(2003).
5
H.-J. Müssig, J. Dabrowski, K. Ignatovich, J. P. Liu, V. Zavodinsky, and
H.-J. Osten, Surf. Sci. 504, 159 (2002).
6
P. Zaumseil, E. Bugiel, J. P. Liu, and H.-J. Osten, Solid State Phenom.
82–84, 789 (2002).
7
A. F. Wells, Structural Inorganic Chemistry (Clarendon, Oxford, 1975).
8
J. Dabrowski and H.-J. Müssig, Silicon Surfaces and Formation of Interfaces (World Scientific, Singapore, 2000).
9
M. Henzler, Prog. Surf. Sci. 42, 297 (1993).
10
A. Fissel, J. Dabrowski, and H. J. Osten, J. Appl. Phys. 91, 8986 (2002).
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VOLUME 85, NUMBER 1
5 JULY 2004
Silicate layer formation at Pr2O3 / Si„001… interfaces
D. Schmeißer
Angewandte Physik-Sensorik, BTU Cottbus, Postfach 10 13 44, D-03013 Cottbus, Germany
H.-J. Müssiga) and J. Dąbrowski
IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany
(Received 30 January 2004; accepted 17 May 2004)
We studied Pr2O3 / Si共001兲 interfaces by synchrotron radiation photoelectron spectroscopy and by ab
initio calculations. We show that the interface formed during molecular-beam epitaxy under the
oxygen partial pressure above 1 ⫻ 10−8 mbar consists of a mixed Si– Pr oxide, such as
共Pr2O3兲共SiO兲x共SiO2兲y. Neither an interfacial SiO2 nor an interfacial silicide is formed. The silicate
formation is driven by a low energy of O in a PrOSi bond and by the strain in the subsurface SiOx
layer. We expect that this natural interfacial Pr silicate will facilitate the integration of the high-k
dielectric Pr2O3 into future complementary metal–oxide–semiconductor technologies. © 2004
American Institute of Physics. [DOI: 10.1063/1.1769582]
about 1 nm to 3 nm were prepared in situ by electron-beam
evaporation of reduced Pr6O11 from a Mo crucible. As a rule,
the sample was kept at 600 ° C, the deposition rate was
0.1 nm/ min, and the O2 partial pressure was in the range of
10−8 mbar. For comparison, some depositions were done on
preoxidized (native oxide) Si共001兲 at room temperature (RT).
The composition of these films was analyzed by SR-PES and
the information on the depth profile was obtained by varying
the photoelectron energy; details of the spectrometer and of
the beam line are given elsewhere.7
Si2p electrons from Si bulk atoms give rise to a characteristic doublet at the binding energy of 99.3 eV. After Pr2O3
deposition, the doublet is still visible (Fig. 1), but it is shifted
by about 2 eV. This shift does not depend on the film thickness, indicating that it is chemical in its nature.8 Moreover,
the shift is clearly different from that known for Si in SiO2
共4 eV兲 and closely resembles the value typical to Pr silicates
共2 eV兲.9 The shift of 4 eV is detectable only when the film is
grown on SiO2.
The oxidation of a Si atom leads to its positive charging
and, consequently, to the increase of the Si2p binding energy
with respect to electrically neutral Si atoms in the Si crystal.
Si atoms in SiO2 have four O neighbors resulting in a Si2p
shift of 4 eV. In a Pr silicate, the four O neighbors of Si have
The main problem arising from the scaling of metal–
oxide–semiconductor (MOS) field effect transistors concerns
a large increase of the leakage current flowing through the
device as the SiO2 gate layer thickness decreases. Therefore,
SiO2 will fail to meet the industrial demands on the leakage
current and long-time reliability, so that another material will
have to be introduced. Its electrical properties will be similar
to those of SiO2 but its dielectric constant k will be up to 10
times higher.1
For ultrathin gate dielectrics, the interface to the Si substrate is a major factor determining the electrical properties
of the MOS structure. In order to maintain a high-quality
interface, a high channel mobility, and good current–voltage
characteristics, it is important to have a low defect density
and no silicide phase at or near the channel interface.
Pr2O3, grown epitaxially on Si共001兲 may possibly replace SiO2 as gate dielectric in sub-0.1 ␮m complementary
MOS technology.2 Here, we analyze the interfacial stoichiometry of the Pr2O3 / Si共001兲 system using synchrotron radiation photoelectron spectroscopy (SR-PES) and ab initio calculations. We arrive at a ternary phase diagram for the
interface composition. The ab initio results allow us to pinpoint some energy factors in the thermodynamics of silicate
and silicide formation and to gain insight into atomic-scale
aspects of the interface.
The calculations were done within the density-functional
theory framework,3 using fhimd.4 We treated trivalent Pr共III兲
with two f electrons in the core and tetravalent Pr共IV兲 with
one f electron in the core as species with distinct pseudopotentials and we calibrated the pseudopotential energy difference between Pr共III兲 and Pr共IV兲 atoms by adding a constant
offset so that the experimental difference in formation enthalpies of bulk Pr2O3 and PrO2 (Ref. 5) is reproduced. The
supercells for interface calculations consisted of six Si layers
covered by up to four Pr oxide layers and passivated by H
atoms on the other side. Calculations for bulk Pr2O3, PrO2,
Pr2Si2O7, and amorphous SiO2 were performed with supercells of approximately 1 ⫻ 1 ⫻ 1 nm3.
In the experiment, Si共001兲 2 ⫻ 1 surfaces were obtained
by a suitable cleaning procedure.6 Films with thickness from
FIG. 1. Si 2p data for an epitaxial Pr2O3 film on Si共001兲 with the thickness
of about 1.5 nm.
a)
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FIG. 2. Emission around the O 1s core level for various Pr2O3 films: (a)
Thick Pr2O3 oxide on SiO2, 600 ° C deposition; 共b1兲 and 共b2兲 epitaxial films
of different thickness, 600 ° C deposition; and (c) SiO2 alloying with Pr2O3,
RT deposition.
Pr neighbors. Since Pr is more electropositive than Si, electron transfer from Pr in Si– O – Pr competes with the electron
transfer from Si, reducing the positive charge of Si and the
Si2p binding energy is decreased.
Associating the 101 eV line with a silicate is consistent
with our observation that after Pr2O3 is deposited at RT on a
preoxidized sample, a similar line develops overnight. The
latter finding means that native SiO2 is thermodynamically
unstable in contact with Pr2O3. Indeed, we do not observe
SiO2 after Pr2O3 deposition on bare substrates. This is a good
news, since a SiO2 interfacial layer would reduce the effective dielectric constant of the stack more dramatically than a
silicate layer does.
These conclusions are further supported by comparison
of the O1s emission from bulklike Pr2O3 deposited on oxidized Si共001兲 at 600 ° C, with the emission typical for the
epitaxial Pr2O3 / Si共001兲 system (Fig. 2). Because the negative charge on O increases from SiO2 through silicates to
Pr2O3, one observes a corresponding decrease of the O 1s
binding energy. RT deposition leads to alloying between
Pr2O3 and SiO2: No Pr2O3 signal is seen.
Finally, we note that while the energy of the silicate Si2p
emission remains constant, its intensity depends on the deposition parameters, the film thickness, and the photon energy.
From these dependencies, we derive the distribution of Si
concentration in the film, and the ternary diagram of the
Si– Pr– O system (Fig. 3). The intensity ratio between the
Schmeißer, Müssig, and Dabrowski
89
Si2p emission of the substrate and of the silicate allows one
to calculate the silicate film thickness; the ratio between the
Si2p and Pr4d emission (not shown) provides information on
the silicate composition. The mole fractions of Pr, Si, and O
calculated in this way are plotted in the phase diagram in
Fig. 3. All data are located within a narrow triangle bordered
by two quasibinary cuts: Between SiO2 and Pr2O3, and between SiO and Pr2O3. The Pr/ Si ratio of unity 共Pr2Si2O7兲 is
observed at the film thickness of about 1 nm and corresponds
to a stable bulk Pr silicate.10 The existence of two quasibinary cuts indicates that the oxygen content in the film depends on the preparation conditions.
We did not observe formation of Pru Si bonds. If such
bonds existed in concentrations above the detection limit, the
phase diagram would contain points starting from SiO2 toward the Si/ Pr= 1 intersection at zero oxygen content. Silicide formation occurs only in the course of vacuum annealing at elevated temperatures.11
A theoretical hint confirming the stability of the film
with respect to silicide formation comes from a comparison
of formation energies of various interfacial structures at different chemical potentials of oxygen, ␮. We define ␮ = 0 for
oxygen in amorphous SiO2 in thermal equilibrium with bulk
Si, that is, 0.5 ␮O2 = 5.2 eV below the computed energy of O
in O2 (the experimental 0.5 ␮O2 is 4.7 eV). We make a simplifying assumption of a chemically sharp Pr2O3 / Si共001兲 interface. A stoichiometric interface corresponds to 50% of the
interfacial bonds being PrSi (silicide type) and 50% being
PrOSi (silicate type). First O atoms are removed from the
film when ␮ drops below ␮PrOPr = −1.6 eV, and are inserted
into interfacial PrSi bonds when ␮ rises above ␮PrOSi
= −0.6 eV. In the oxygen-rich regime above, ␮SiOx ⬇ 1.0 eV,
Siu Si bonds of the substrate are oxidized and strained SiOx
is formed. The charge state of all Pr atoms remains +3.
Since the energy of O is lower between Pr and Si atoms
than between Si atoms (by 0.6 eV), a silicide can be formed
only when not enough O is available. Otherwise, O is extracted from Siu O u Si bonds and inserted between Si and
Pr, reducing the Si (sub)oxide and oxidizing the silicide.
Pr silicate begins to form when first SiO2 molecules dissolve in the Pr2O3 film. This corresponds to substitution of
two O−2 atoms by 共SiO4兲−4. In other words, two O atoms are
removed from the Pr2O3 film to the reservoir of O with energy ␮, a Si atom is added from Si bulk, and four O atoms
are taken from the reservoir and placed between Pr and Si. If
Si is in equilibrium with bulk Si, Pr is in equilibrium with
Pr2O3, and O is in equilibrium with the reservoir, we can
now estimate the silicate formation energy E f from:
E f = 共2␮PrOPr − 2␮兲 + 共4␮ − 4␮PrOSi兲 ⬇ 2共␮ − 0.4兲 eV,
共1兲
FIG. 3. The ternary phase diagram of the Siu O u Pr system.
114
where the energy of O is approximated by ␮PrOPr. A positive
E f means that the silicate is stable. The conclusion is that
already at ␮o ⬇ 0.4 eV a process collecting two O atoms on a
Si atom and dissolving the resulting SiO2 moiety in the
Pr2O3 film becomes energetically favorable, due to the low
energy of oxygen between Pr and O atoms 共␮PrOSi兲. Since
␮o ⬇ ␮SiOx, the dissolution of oxidized Si in the epitaxial
Pr2O3 is promoted by the elastic stress in the native oxide.
On the other hand, calculations for bulk Pr2Si2O7, Pr2O3, and
amorphous SiO2 show that the mixing of the bulk materials
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FIG. 4. A SiO2 moiety dissolved in ultrathin Pr2O3 film (a) causes the
surface to buckle. (b) Filling the trenches with 0.5 monolayer Pr2O3 flattens
the surface and reduces the energy. Si is shown white, O is light gray, Pr is
dark gray.
is favorable by about 1 eV per Si atom. This means that the
interfacial Pru O u Si bonds are strained.
We now consider the structures associated with epitaxial
silicate. We computed total energies for numerous models of
interfacial silicates with various stoichiometries, atomic arrangements, and lateral periodicities (from 3 ⫻ 1 to 3 ⫻ 3,
measured in Si共001兲 surface lattice periodicity). Some of
these structures are remarkably stable, becoming the favorable phase at ␮ ⬎ 0.5 eV, i. e., before Si is oxidized to SiOx.
This value is close to ␮o, indicating that the Pru O u Si
bonds in these structures are as strained as at the interface.
The estimate of Eq. (1) is further confirmed by a direct
calculation for a single SiO2 molecule dissolved in a three
monolayer thick Pr2O3 / Si共001兲 film. The silicate formation
begins at ␮1 = 1.05 eV when film surface is allowed to buckle
due to the additional volume introduced by the SiO2 molecule, and at ␮2 = 0.55 eV when the surface is smoothed by
depositing half a monolayer of Pr2O3 (Fig. 4). The corresponding energy difference ⌬E f = 2共␮1 − ␮2兲 = 1.0 eV turns
out to be equal to ⌬E0.5 = E3.5 − E4 = E3.5 − E3, where En is the
energy of the film with n atomic layers of Pr2O3.
A high Si concentration in the silicate is stabilized if the
Si atoms are intercalated between Pr2O3 planes, forming a
stacked structure. An example corresponding to the Si/ Pr
ratio of 3, is shown in Fig. 5. Above ␮3 ⬇ 0.8, this structure
has a lower energy than Pr2O3 / Si共001兲, and above ␮4 ⬇ 1.0 it
becomes the lowest-energy interfacial silicate among the
structures considered by us. Note that not all Siu Si bonds
in this silicate are oxidized; a complete oxidation is difficult
without simultaneous excessive oxidation of the substrate.
Since ␮3 is relatively high and numerous Pru O u Si bonds
in the film are strained, we expect that these Siu Si bonds
are weak spots: When some of them are broken, the film may
lower its energy by relaxation of the accumulated strain.
We conclude with the following summary:
(1) Oxidation of the substrate during Pr2O3 deposition from
a Pr6O11 source produces a stable silicate buffer layer.
(2) A substantial Pr content in the buffer makes the capaci-
FIG. 5. A hypothetical intercalated silicate at the interface between Pr2O3
and Si共001兲. Si is white, O is light gray, Pr is dark gray. Note the presence
of Siu Si bonds in the film.
tance loss due to the presence of the buffer less severe.
(3) A substantial SiO2 content in the buffer should facilitate
structural accommodation of the film to the substrate.
(4) Siu Si bonds in the buffer may lead to strain-induced
dangling bond formation and charge trapping.
This work was financially supported by the Deutsche
Forschungsgemeinschaft. Calculations were performed on
Cray-T3E supercomputer cluster in von Neumann Institute
for Computing, Jülich, Germany (Project No. HFO06).
1
G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 89, 5243
(2001).
H.-J. Müssig, H. J. Osten, E. Bugiel, J. Dąbrowski, A. Fissel, T. Guminskaya, K. Ignatovich, J. P. Liu, P. Zaumseil, and V. Zavodinsky, 2001
IEEE International Integrated Reliability Workshop—Final Report (IEEE,
New York, 2001), p. 1.
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A. Fissel, J. Dąbrowski, and H. J. Osten, J. Appl. Phys. 91, 8968 (2002).
4
M. Bockstedte, A. Kley, J. Neugebauer, and M. Scheffler, Comput. Phys.
Commun. 107, 187 (1997).
5
H. Bergman, Gmelin Handbuch der Anorganischen Chemie, Seltenerdelemente, Teil C1 (Springer, Berlin, 1974).
6
B. S. Swartzentruber, Y.-W. Mo, M. B. Webb, and M. G. Lagally, J. Vac.
Sci. Technol. A A7, 2901 (1989).
7
D. R. Batchelor, R. Follath, and D. Schmeißer, Nucl. Instrum. Methods
Phys. Res. A 467, 470 (2001).
8
C. D. Wagner, W. M. Riggs, L. E. Davis, and J. F. Moulder, Handbook of
X-ray Photoelectron Spectroscopy (Perkin–Elmer, Eden Prairie, MN,
1978).
9
J. X. Wu, Z. M. Wang, M. S. Ma, and S. Li, J. Phys.: Condens. Matter 15,
5857 (2003).
10
J. Felsche, Z. Kristallogr. 133, 304 (1971).
11
H.-J. Müssig, J. Dąbrowski, K. Ignatovich, J. P. Liu, V. Zavodinsky, and
H. J. Osten, Surf. Sci. 504, 159 (2002).
2
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Optical Materials xxx (2004) xxx–xxx
www.elsevier.com/locate/optmat
Silicon-based light emission after ion implantation
M. Kittler
b
a,c,*
,
T. Arguirov
b,c
, A. Fischer a, W. Seifert
a,c
a
IHP microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
BTU Cottbus, Lehrstuhl Experimentalphysik II, Materialwissenschaften, Universitätsplatz 3-4, 03044 Cottbus, Germany
c
IHP/BTU Joint Lab, Universitätsplatz 3-4, 03044 Cottbus, Germany
Abstract
Electroluminescence of boron and phosphorus implanted samples has been studied for various implantation and annealing conditions. Phosphorus implantation is found to have a similar effect on light emission as boron implantation. The band-to-band luminescence of phosphorus implanted diodes is observed to increase by more than one order of magnitude upon rising the sample
temperature from 80 K to 300 K and a maximum internal quantum efficiency of 2% has been reached at 300 K. The remarkably high
band-to-band luminescence is attributed to a high bulk Shockley–Read–Hall lifetime, likely promoted by the gettering action of the
implanted phosphorus. The anomalous temperature behavior of the efficiency can be explained by a temperature dependence of the
lifetime characteristic of shallow traps.
2004 Published by Elsevier B.V.
1. Introduction
There is substantial need for efficient light emitters
that are compatible with standard silicon-based integrated circuit technology for development of on-chip
optical interconnection. Ng et al. [1] demonstrated that
light-emitting diodes (LED) operating efficiently at
room temperature can be formed by implantation of
boron into silicon.
Recently, we found that such light emission can also
be produced after phosphorus implantation into p-type
Si [2]. Fig. 1 shows electroluminescence (EL) data measured on a n+–p diode under forward bias. Detailed
investigations by photoluminescence (PL) revealed that
the luminescence spectrum of implanted Si samples consists of the band-to-band line (BB) and the defect-band
lines (D1–D4), see e.g. [2]. The intensity of the BB line
was observed to become stronger with increasing temperature whereas the intensity of the D-lines decreased.
*
Corresponding author. Tel.: +49 335 5625 130; fax: +49 335 5625
333.
E-mail address: [email protected] (M. Kittler).
At room temperature, the BB line is found to dominate,
with no D lines detectable. The achievement of the
strong room temperature luminescence (and of the
anomalous temperature behavior of the luminescence)
has been attributed in Ref. [1] to the formation of
implantation related dislocation loops and the introduction of a local strain field that modifies the Si band structure and provides spatial confinement of charge carriers,
thus preventing non-radiative recombination. This
explanation is not convincing to us. Indeed, it is known
that the local strain field at dislocations causes a modification of the band structure, namely the formation of
shallow one-dimensional bands about 80 meV from the
valence and the conduction bands, respectively (see
Ref. [3] and references therein). However, the onedimensional dislocation-related bands do not form the
band-to-band line. It is well accepted that they are the
cause for the D4 line which is shown in the low-temperature EL spectrum given in the insert of Fig. 1. Accordingly, dislocations should not be the (direct) cause for
the strong luminescence in ion implanted Si. The goal
of this work is to improve the understanding of the origin of the implantation induced BB light emission, in or-
0925-3467/$ - see front matter 2004 Published by Elsevier B.V.
doi:10.1016/j.optmat.2004.08.045
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0.7
0.6
0.5
0.4
BB
Electroluminescence
Internal efficciency, %
0.8
300K
D4
80K
0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25
0.3
Photon energy, eV
0.2
0.1
0.0
50
Phosphorous implant
100
150
200
Temperature, K
250
300
Fig. 1. Temperature dependence of the integrated intensity of the
band-to-band electroluminescence of a n+–p diode. The inset shows
the EL spectra at 300 K and 80 K, respectively.
der to provide ways for a further increase of room temperature luminescence.
2. Experimental
Si epilayers of a few micrometer thickness were
grown by chemical vapor deposition on (1 0 0) oriented
8 in. Czochralski-grown silicon wafers. The resistivity
of the substrates and of the epilayers was about
10 X cm and the conductivity was either n- or p-types.
Implantation was performed through a 15 nm scattering
oxide. Boron was implanted into the n-type material at
energies ranging from 50 to 250 keV and doses from
2 · 1012 to 2 · 1014 cm2, while phosphorus was implanted into the p-type material at energies between
135 and 500 keV and doses in the range from 4 · 1012
to 4 · 1014 cm2. After implantation, the samples were
heat treated in a furnace at 1000 C for 20 min in nitrogen atmosphere or by rapid thermal annealing (RTA) at
1040 C for 10 s in nitrogen atmosphere, respectively. Finally, the wafers received a 400 C/30 min anneal in
hydrogen atmosphere. This way p–n junctions were
formed in the wafers. After the annealing step crystal defects were observed in the samples, predominantly at the
depth of the maximum dopant concentration. The defect
density was higher for larger implantation doses. Examples of an analysis by transmission electron microscopy
(TEM) can be found in Ref. [4].
Luminescence was measured in the temperature
range between 80 and 300 (330) K. For PL, an argon laser (514 nm) was used for excitation. The ohmic contacts
needed for EL investigations were prepared by evaporating Al on the front side of the samples and rubbing
a Ga/In eutectic on the rear side. A 1-mm2 opening in
the aluminium layer was left as a window for the lumi-
120
nescence measurement. Forward biases up to 1.5 V were
applied to the LED structures to inject excess charge
carriers. The current densities were in the range of one
to a few tenths of A/cm2. All measurements were done
at a modulation frequency of 30 Hz.
Absolute light power measurements were realized by
comparing the diode spectrum with the spectrum of a
commercially
available
infrared
emitter
with
k = 950 nm and known emitter characteristics. For correct absolute luminescence measurements, the ratio of
the systemÕs spectral responsivity at 950 nm and
1127 nm (BB line) was taken into account. The spectral
responsivity was determined by measurements on a
black body emitter at 3000 K. The power of the BB line
emission was obtained by integrating over the whole
band edge luminescence peak in the spectrum. The internal quantum efficiency was calculated from the measured external efficiency by ginternal = gexternal/0.013,
which takes into account the refractivity of Si.
3. Results
PL measurements revealed the existence of the bandto-band line and also D band luminescence originated
by crystal defects/dislocations. The peak energy of the
BB line (wavelength around 1.1 lm) shifts to smaller
energies with increasing temperature. The temperature
behavior of the peak position follows the behavior of
the band gap. The difference between the energy of the
band-to-band line and the band gap corresponds to
the energy of the transverse optical (TO) phonon.
Accordingly, the band-to-band line can be described as
a one-phonon line. On the low-energy shoulder also
the two-phonon line becomes visible. Its intensity is
about one order of magnitude smaller than that of the
one-phonon line. Further details about PL observations
are given in Ref. [2].
Fig. 2 shows the internal quantum efficiency of EL
under identical conditions (IF 0.8 A cm2) at room
temperature for different boron implanted p+–n LED.
A clear influence of the implantation conditions and
the annealing can be seen. Furnace anneal causes always
a higher efficiency than RTA for identical implantation
conditions. The highest efficiency in our boron implanted samples—close to 1%—appears for 50 keV, i.e.
for the smallest implantation energy, and at the highest
implantation dose of 2 · 1014 cm2. This trend, i.e. increase of efficiency with decreasing energy and increasing dose, is in agreement with data reported in Ref. [1]
where an efficiency of about 1.6% was measured at room
temperature for boron implantation at 30 keV and
1 · 1015 cm2.
Fig. 3 shows the maximum internal quantum efficiencies of EL at room temperature that were obtained for
different phosphorus implanted n+–p LED. Again fur-
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B, 240 keV
RTA
Furnace
B, 50 keV
RTA
Furnace
with the energy given to a third carrier and the radiative
band-to-band recombination [5]. The recombination
rates R of these mechanisms depend on the excess carrier
concentration Dn in the following manner
for the SRH recombination rate
B, 30 keV
Furnace
2%
RSRH ¼ Dn 1=sSRH ;
1x1015 cm-2
2x1014 cm-2
2x1012 cm-2
0%
Fig. 2. Internal quantum efficiency (T = 300 K) of the band-to-band
EL of boron implanted p+–n diodes for different implantation and
annealing conditions. The efficiency is larger for small implantation
energies and increases with the implantation dose. For comparison,
experimental data reported by Ng et al. [1] is given, too.
η internal
2%
P, 500 keV P, 135 keV
14
-2
4x10 cm 4x1013 cm-2
1%
Furnace
0%
RTA
Fig. 3. Internal quantum efficiency of the band-to-band EL of
phosphorus implanted n+–p diodes at T = 300 K, for different implantation and annealing conditions. Furnace anneal and low implantation
energy yield the best results.
nace anneal is found to yield a higher efficiency than
RTA. Also, reduction of implantation energy and increase of implantation dose result in an increase of efficiency. An efficiency higher than 1.5% was measured for
135 keV and 4 · 1013 cm2. By optimizing the P implantation (lower energy and higher dose) we believe to be
able to increase the light emission efficiency at 300 K
to 5%. The best value we could reach until now at room
temperature for phosphorous implanted diodes is about
2%.
ð1Þ
for the radiative recombination rate
RBB Dn2 B;
ð2Þ
and for the Auger recombination rate
RAuger Dn3 C:
ð3Þ
The inverse of the SRH lifetime,sSRH, is the rate
determining coefficient in (1). Note that 1/sSRH is proportional to the concentration Nimp of deep levels/impurities. B denotes the radiative recombination coefficient
in (2) and C is the Auger recombination coefficient in
(3).The radiative recombination coefficient B (for the
band-to-band recombination) was experimentally determined in perfect Si to be 1014 cm3 s1 at 300 K [6]. For
Auger recombination, the coefficients for electrons and
holes differ slightly. In the estimate shown below, we
have used a mean value of C 1031 cm6 s1 at 300 K
[7].
The internal quantum efficiency is defined by the ratio
of the radiative recombination rate RBB and the overall
recombination rate, i.e.
gi ¼ RBB =ðRSRH þ RBB þ RAuger Þ:
ð4Þ
Fig. 4 depicts the calculated internal quantum efficiency gi as a function of the excess charge carrier
density Dn according to (4). The calculation was done
τ SRH
1 ms
100 µs
0.1
internal
1%
target 5%
P: 135 keV
η
η internal
3
0.01
F
F
F
RTA
30 µs
1E-3
1E16
10 µs
B: 30 keV, W.L. Ng et al.
P: 500 keV
1E17
1E18
-3
∆n (cm )
4. Discussion
4.1. Model
Recombination in Si consists of three components,
each associated with a distinct mechanism, namely multiphonon or Shockley–Read–Hall (SRH) recombination
via deep levels in the band-gap, Auger recombination
Fig. 4. Internal quantum efficiency gi vs excess carrier concentration
Dn, calculated using relation (4) with SRH lifetime sSRH as parameter.
Experimental data points for n+–p diodes implanted with phosphorus
at energies of 135 keV and 500 keV, respectively, are indicated, together
with data from Ng et al. [1]. Solid symbols refer to furnace annealing,
open symbols to RTA. The position of the experimental data in the gi
vs Dn plot allows to judge about the SRH lifetime. An efficiency target
of 5% is believed to be reachable for phosphorus implantation.
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for 300 K by using the above given values for the coefficients B and C, with the SRH lifetime sSRH as
parameter.
4.2. Efficiency of light emission
The efficiency for light emission is largely governed
by the SRH lifetime, i.e. the quality of the Si material.
In nearly perfect Si material with sSRH = 103 s, the
maximum of the quantum efficiency gi is expected to
reach about 30%. This value is in agreement with Trupke et al. [8] who concluded from their experimental
data that the internal quantum efficiency of Si at room
temperature may exceed 20%.
The second factor of importance for radiative recombination is the excess carrier density Dn. High Dn values
can be reached in the case of EL, sufficiently large forward bias exceeding the diffusion voltage of the p–n
junction (UF > Ud) provided. Under such bias conditions, the densities of both majority and minority carriers in the base region of the diode close to the junction
become larger than the equilibrium density of the majority carriers, see e.g. Spenke [9]. According to diode simulations, excess electron and hole densities (Dn, Dp,
Dn Dp) exceeding the doping level in the diode base
by a factor of 100 can be reached in our n+–p diode at
UF > Ud. The same is true for p+–n diodes produced
by B implantation.
4.3. Influence of implantation and annealing
Excess Carrier Density ∆n (cm–3)
Results of a calculation for n+–p diodes obtained
with the process and device simulator ‘‘ISE TCAD’’
17
10
P Implant: 135 keV
Furnace
RTA
500 keV
16
2 x 10
13
10
UF = 1.2 V
T = 300 K
14
10
Implantation Dose (cm-2 )
5 x 1014
Fig. 5. Excess carrier density in the base of our n+–p diodes vs
phosphorus implantation dose, calculated with a process and device
simulator ‘‘ISE TCAD’’ for a diode forward bias of 1.2 V. A (1 0 0)
substrate with a boron doping concentration of 5 · 1014 cm3 was
assumed. The curves were obtained for an implantation energy of
135 keV. Implantation at 500 keV leads to lower carrier densities (see
data points at the right). The furnace anneal is found to result in higher
excess carrier concentrations than RTA.
122
are given in Fig. 5. We assumed phosphorus implantation at 135 keV, a (1 0 0) substrate with a boron concentration of 5 · 1014 cm3, annealing according to the
conditions given above in ‘‘Experimental’’, and a diode
forward bias of 1.2 V. The calculations show that the excess carrier density Dn in the base increases with the
implantation dose. Furthermore, furnace anneal yields
a higher excess carrier density than RTA. This means
that the phosphorus depth profile resulting from furnace
anneal produces a higher emitter efficiency than the corresponding RTA profile.
4.4. Analysis of experimental data
Here we will analyze phosphorus implanted samples
in detail. The internal quantum efficiency was measured
at room temperature under a forward bias of about
1.2 V. After implantation at 500 keV with a dose of
4 · 1014 cm2 we found an efficiency of about 1.16%
for the furnace annealed sample and about 0.6% for
the RTA sample. By applying the process and device
simulator we calculated an excess carrier density, Dn,
of 1.2 · 1017 cm3 for the furnace annealed sample and
of 5 · 1016 cm3 for the RTA sample, respectively, for
the above given conditions. The corresponding data
points are presented in the gi vs Dn plot of Fig. 4 as full
and open circles, respectively. According to these data,
we may expect a SRH lifetime slightly above 10 ls in
the p-type base region of the n+–p diode. Data points
for samples that were implanted with phosphorus at
135 keV and a dose of 4 · 1013 cm2 are also shown in
Fig. 4. Again, the furnace annealed sample is shown as
full circle and the RTA sample as open circle. In this
case the SRH lifetime is expected to be roughly 30 ls.
The higher lifetime in the 135 keV/4 · 1013 cm2 samples
might be due to a more efficient phosphorus gettering as
compared to the 500 keV/4 · 1014 cm2 samples.
EBIC measurements (see Ref. [10]) of the P implanted
samples yielded a lower limit for the diffusion length of
electrons (minority carriers) of Ln 200 lm in the ptype base. This value corresponds to a lifetime of
sn 10 ls indicative of a high material quality and is
in agreement with our expectations, although a direct
comparison between lifetimes under conditions of EL
and EBIC is difficult.
We also have analyzed the data of Ng [1] given for a
LED formed by implantation of boron at 30 keV with a
dose of 1 · 1015 cm2 in n-type Cz–Si substrate followed
by furnace anneal. The room temperature efficiency of
the LED was reported to be about 1.6% and the lifetime
of 18 ls was measured in base region. For the given
implantation and annealing conditions we obtained an
excess carrier density of Dn = 2 · 1017 cm3 from process
and device simulation for a bias of UF = 1.2 V. The corresponding data point of this sample is presented in Fig.
4 as a full square. Accordingly, we expect a SRH lifetime
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100
∆E = 45meV
low injection
β = 0.01
τ /τ (100Κ)
5
mately according to B(T) / (300 K/T)
[13].
Nevertheless, the lifetime increase overcompensates the
decrease of B(T). Thus, the description based on relations (1)–(4) allows to explain the anomalous temperature behavior of the light emission efficiency shown
e.g. in Fig. 1. Hence, this, modelÕ does not require a
quantum confinement at dislocations to explain the efficient light emission from Si, as suggested in Ref. [1].
Even the existence of spatial indirect excitons, mentioned by Sun et al. [14], seems not to be necessary for
explanation of the anomalous temperature behavior.
3/2
10
high injection
β = 100
1
100
150
200
250
300
T (K)
Fig. 6. Temperature behavior of the SRH lifetime calculated for
shallow traps with an energetic position of DE = 45 meV from the band
edge. The lifetime is found to increase with temperature for both, low
injection (b = 0.01) and high injection (b = 100).
of approximately 10 ls in the n-type base region of the
diode. This value is close to the lifetime of 18 ls that
was determined directly (see Ref. [1]).
4.5. Anomalous temperature behavior of light emission
For excess carrier densities of about Dn < 1017 cm3,
the total recombination in Si is dominated by the SRH
recombination even at strong radiative recombination,
i.e. also at highly efficient light emission. Consequently,
the temperature behavior of the light emission efficiency
gi(T) is strongly affected by the temperature behavior of
the SRH-lifetime sSRH(T). An increase of gi with temperature will appear if sSRH increases upon increase of temperature. Indeed, according to the SRH statistics sSRH
increases with temperature if shallow levels dominate
the recombination. Fig. 6 shows the temperature behavior sSRH(T) which has been calculated for shallow traps
with an energy position in the band gap 45 meV from
the band edge (for example substitutional boron or phosphorus atoms in the Si lattice, respectively). Note that the
concept of dopants as shallow recombination centers was
successfully demonstrated already in [11]. Calculations
about the temperature and injection dependence of the
lifetime sSRH made on basis of the SRH statistics—taking
into account the trap position in the forbidden gap—have
been described in [12], for example. The dependencies
shown in Fig. 6 are calculated in the same manner. They
show that at low injection—b = 0.01 (b denotes the ratio
between the excess and equilibrium carrier density)—the
lifetime increases by a factor >100 between 100 and
300 K, and even for high injection—b = 100—there still
appears a lifetime increase by a factor of about 10.
On the other hand, the radiative recombination coefficient drops upon increase of temperature approxi[9] E. Spenke, in: W. Heywang and R. Müller, (Eds.), ‘‘pnÜbergänge’’, Band 5 in series, Halbleiter-ElektronikÔ, SpringerVerlag, Berlin–Heidelberg–New York (1979).
[10] C.J. Wu, D.B. Wittry, J. Appl. Phys. 49 (1978) 2827.
[11] H.J. Leamy, L.C. Kimerling, S.D. Ferris, in: O. Johari (Ed.),
Proc. Workshop on Microelectronic Device Fabrication and
5. Summary
We can state that the experimental efficiency data fit
well with the gi vs Dn plot shown in Fig. 4. This holds
for the influence of annealing (furnace vs RTA), for the
influence of implantation energy and dose and also for
data of the boron implanted diode given in the literature.
Moreover, a tentative explanation of the anomalous temperature behavior of the light emission could be given.
This demonstrates that high luminescence may satisfactorily be explained by high bulk SRH lifetimes and large
excess carrier densities that can be reached by forward
biasing of the LED. Accordingly, we believe that a room
temperature efficiency in the range of 5% is a value that
might be realized, see also Fig. 4.
Acknowledgement
The financial support for this research by the HWP
grant of the Federal Government of Germany and the
State of Brandenburg is gratefully acknowledged.
References
[1] W.L. Ng, M.A. Lourenco, R.M. Gwilliam, S. Ledain, G. Shao,
K.P. Homewood, Nature 410 (2001) 192.
[2] M. Kittler, T. Arguirov, W. Seifert, SPIE Proc. Int. Soc. Opt.
Eng. 5327 (2004) 164.
[3] V. Kveder, M. Kittler, W. Schröter, Phys. Rev. B 63 (2001)
115208.
[4] T. Arguirov, M. Kittler, W. Seifert, D. Bolze, K.E. Ehwald, P.
Formanek, J. Reif, in: H. Richter, M. Kittler (Eds.), Proc. 10th
International Autumn Meeting on Gettering and Defect Engineering in Semiconductor Technology (GADEST 2003), Solid
State Phenom. 95–96 (2004) 289.
[5] D.K. Schroder, in: M. Kittler (Ed.), Proc. 3rd International
Autumn Meeting on Gettering and Defect Engineering in Semiconductor Technology (GADEST Õ89), Solid State Phenom. 6–7
(1989) 383.
[6] H. Schlangenotto, H. Maeder, W. Gerlach, Phys. Stat. Sol. (a) 21
(1974) 357.
[7] J. Dziewior, W. Schmid, Appl. Phys. Lett. 31 (1977) 346.
[8] T. Trupke, J. Zhao, A. Wang, R. Corkish, M.A. Green, Appl.
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[12] M. Kittler, W. Seifert, Phys. Stat. Sol. (a) 138 (1993) 687.
[13] R.N. Hall, Proc. Inst. Elect. Eng. 106B (17) (1960) 983.
[14] J.M. Sun, T. Dekorsky, W. Skorupa, B. Schmidt, M. Helm,
Appl. Phys. Lett. 83 (2003) 3885.
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Erschienene Publikationen
Published Papers
Erschienene Publikationen
Published Papers
(1)
Distribution and Properties of Oxide Precipitates in Annealed Nitrogen-doped 300 mm
Si Wafers
V.D. Akhmetov, H. Richter, W. Seifert, O. Lysytskiy, R. Wahlich, T. Müller, M. Reiche
European Journal of Applied Physics 27, 159
(2004)
Spatial distribution and properties of oxide were examined in 300 mm nitrogen (N) doped CZ-Si. Experimentally grown materials with N ranging from 1013 cm -3
to 1015 cm -3 were studied by infrared light scattering
tomography, scanning infrared microscopy, transmission electron microscopy and electron beam induced
current. It was established that an increasing N content improves the uniformity of the radial distribution
of precipitates in the bulk of the wafer, the density of
precipitates reaching a level of 10 9 cm -3. The width of
the denuded zone varies in the range from 15 µm to
70 µm depending on radial position and N doping level.
Electron microscopy revealed lower oxide precipitate
densities of about 10 5 to 10 8 cm -3. The results are interpreted in terms of existence of agglomerates of nanometer size precipitate nuclei and/or by the defectinduced strain relaxation around the precipitates.
(2)
Effects of Various Ci/Ti and Co/TiN Layer
Stacks and the Silicide Rapid Thermal Process Conditions on Cobalt Silicide Formation
S. Buschbaum, O. Fursenko, D. Bolze, D. Wolansky, V. Melnik, J. Nieß, W. Lerch
Microelectronic Engineering 76, 311 (2004)
is for the Co/ Ti layer stacks. After the subsequent
selective etch step the second RTP step (RTP2) was
performed at 800°C for 30 s. Rs after RTP2 strongly
depends on the initial Co thickness and its uniformity
for both systems if the RTP1 temperature was above
470°C. For the Co/ TiN layer stacks the final Rs results are not influenced by the RTP1 temperature or
its uniformity (above 470°C). In this case silicidation
is independent of the cap thickness. However, in the
Co/ Ti system the reactive Ti influences the silicidation process by reducing the amount of available Co in
a manner that depends on the RTP1 temperature and
the Ti cap thickness.
(3)
The effect of aluminum gettering on different silicon
materials used for solar cells has been investigated by
means of microwave photoconductivity decay (µ-PCD)
and electron beam induced current (EBIC). µ-PCD
measurement revealed that the lifetime of multicrystalline silicon (mc-Si) with a lower initial lifetime could
be increased by high temperature gettering (1000°C),
while that of mc-Si with a higher initial lifetime could
not be increased, but was even degraded. EBIC results revealed that no significant improvement of diffusion length was observed in both contaminated and
uncontaminated wafers, while 850°C Al gettering was
employed. It is concluded that both the initial material
quality and the thermal treatment have influences on
the effect of Al gettering. In addition, dislocations with
bright EBlC contrast were discovered in annealed mcSi wafers, the origin of which is discussed.
(4)
The effects of cap layer type (Ti or TiN) and its thickness, Co thickness and rapid thermal processing (RTP)
temperature on cobalt silicide formation are investigated by a combination of electrical and optical measurements. Various Co/TiN and Co/Ti layer stacks (thicknesses 8-20 nm per layer) were deposited on (100) Si
substrates. The first RTP step (RTP1) was performed
by isochronal annealing at various temperatures between 400 and 600°C for 30 s. It was observed that
the temperature range for constant sheet resistance
(Rs) values after the first RTP step (RTP1 process window) is smaller for the Co/ TiN layer stacks than it
124
Aluminum Gettering in Photvoltaic Silicon
J. Chen, D. Yang, X. Wang, D. Que, M. Kittler
European Physical Journal of Applied Physics
27, 119 (2004)
Assessing the Performance of Two-Dimensional Dopant Profiling Techniques
N. Duhayon, P. Eyben, M. Fouchier, T. Clarysse, W. Vandervorst, D. Alvarez, S. Schoemann,
M. Ciappa, M. Stangoni, W. Fichtner, P. Formanek,
M. Kittler, V. Raineri, F. Giannazzo, D. Goghero,
Y. Rosenwaks, R. Shikler, S. Saraf, S. Sadewasser,
N. Barreau, T. Glatzel, M. Verheijen, S.A.M. Mentink, M. von Sprekelsen, T. Maltezopoulos, R. Wiesendanger, L. Hellemans
Journal of Vacuum Science & Technology B 22
(1), 385 (2004)
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This article discusses the results obtained from an
extensive comparison set up between nine different
European laboratories using different two-dimensional
(2D) dopant profiling techniques (SCM, SSRM, KPFM,
SEM, and electron holography). This study was done
within the framework of a European project (HERCULAS), which is focused on the improvement of 2Dprofiling tools. Different structures (staircase calibration samples, bipolar transistor, junctions) were used.
By comparing the results for the different techniques,
more insight is achieved into their strong and weak
points and progress is made for each of these techniques concerning sample preparation, dynamic range, junction delineation, modeling, and quantification.
Similar results were achieved for similar techniques.
However, when comparing the results achieved with
different techniques differences are noted.
(5)
Electron Holography on Silicon Microstructures: A Comparison with Scanning Probe
Techniques
P. Formanek, M. Kittler
Journal of Physics: Condensed Matter 16, 193
(2004)
Two-dimensional dopant profiling is being strongly demanded by the semiconductor industry, and several
techniques have been developed in recent years. We
compare the performance of electron holography in
a transmission electron microscope with other microscopic techniques. The advantages of electron holography are the high spatial resolution of a few nanometres and the direct interpretability of the measured
two-dimensional electrostatic potential requiring no simulation. We demonstrate the detection of a 0.5 monolayer of boron in silicon and silicon germanium. We
image a 35 nm wide potential dip of 25 mV in a boron-doped specimen, corresponding to detection of a
2 x 1017 B cm -3 dip between peaks of 2 x 1018 B cm -3.
Moreover, we illustrate directly by electron holography
the existence of a potential barrier at NiSi2 precipitates
in silicon, which was predicted earlier by the electronbeam-induced current technique.
(6)
Development of Spectroscopic Ellipsometry
as in-line Control for Co SALICIDE Process
O. Fursenko, J. Bauer, A. Goryachko, D. Bolze,
P. Zaumseil, D. Krüger, D. Wolansky, E. Bugiel,
B. Tillack
Thin Solid Films 450, 248 (2004)
Published Papers
This work is aimed at in-line thickness and composition analysis of Co silicides by spectroscopic ellipsometry (SE). The silicides were formed by a two-step
rapid thermal annealing (RTA) in nitrogen at different
temperatures from initial Co layers deposited on Si
(100) substrates and capped by a protective layer
of TiN. The optical constants of Co, CoSi and CoSi
films were calculated in the wavelength range of 240 x
800 nm, describing the optical dispersions by harmonic oscillator models. These models were applied for
in-line thickness and composition control of the main
steps of Co SALICIDE process. The effects of the first
RTA temperature and initial Co thickness on formation
of silicide phases and their thickness were evaluated.
For phase identification, additional methods (sheet resistance, Auger electron spectroscopy and X-ray diffraction) were used. Finally, the suitability of SE for
layer thickness uniformity evaluation was demonstrated for the main steps of Co SALICIDE process.
(7)
Raman Investigation of Stress and Phase
Transformation Induced in Silicon by Identation at High Temperatures
S. Kouteva-Arguirova, V. Orlov, W. Seifert,
J. Reif, H. Richter
European Physics Journal – Applied Physics 27
(1-3), 279 (2004)
To study the material deterioration at and around the
support contacts during processing of silicon wafers,
we used Rockwell indentation at elevated temperatures
as a model. Cz-silicon was subjected for 30 s to a load
of 1.5 N, at temperatures between 70°C and 660°C.
The resulting morphology was checked by scanning
electron microscopy. Micro Raman spectroscopy was
used to monitor residual stress and the occurrence
of silicon polymorphs. We found strong compressive
stress inside the indented area, with a dramatic drop
and reversal to tensile stress at its boundary. The morphology shows a top hat profile, covered with a mesh
of vein-like structures. Crystalline phases such as Si-III,
Si-IV, Si-XII, and amorphous silicon are observed. Outside the spot, the situation depends strongly on the
indentation temperature. Up to 400°C the material appears practically unstressed, with a high density of
relaxation cracks. At 500°C and 600°C a transition is
found from strong tensile stress at the boundary to
another region of compressive stress extending over
more than 40 µm, associated with a significantly lower crack density. At still higher temperature (660°C)
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the crack density tends to zero, and comparably weak
stress seams to oscillate between compressive and
tensile.
(8)
Baseband Processor for IEEE 802.11a Standard with embedded BIST
M. Krstic, K. Maharatna, A. Troya, E. Grass,
U. Jagdhold
Facta Universitatis, Series: Electronics and
Energetics 17, 231 (2004)
In this paper results of an IEEE 802.11a compliant lowpower baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for
testability strategy based on Built-In Self-Test (BIST) is
proposed. Finally, implementational results and power
estimation are reported.
(9)
Characterization of Ge Gradients in SiGe
HBTs by AES Depth Profile Simulation
D. Krüger, A. Penkov, Y. Yamamoto, A. Goryachko, B. Tillack
Applied Surface Science 224 (1-4), 51 (2004)
We show that AES depth profiling extended by a simple profile simulation technique allows characterization
of details in the Ge concentration gradients for SiGe
hetero-bipolar transistors (HBTs). Using the mixingroughness-information depth (MRI) model to simulate the experimental data allows us to reveal concentration steps with a precision of about +or-2 at.% and
small deviations from linear concentration gradients.
The obtainable high lateral resolution of AES facilitates
an application for process optimization and control in
small microelectronic structures.
(10) Diffusion and Segregation of Shallow As
and Sb Junctions in Silicon
D. Krüger, H. Rücker, B. Heinemann, V. Melnik,
R. Kurps, D. Bolze
Journal of Vacuum Science and Technology 22
(1), 455 (2004)
The diffusion and segregation of Sb and As is investigated after low-energy implantation and annealing,
both rapid thermal processing and furnace annealing.
We demonstrate that the absence of transient enhanced diffusion effects for Sb facilitates the fabrication
of signifi cantly shallower junctions with less dopant se-
126
gregation to the surface. It is shown that Sb implantation can be used to fabricate low-resistivity ultrashallow
junctions suitable for source/drain extensions in n-type
metal-oxide-semiconductor field effect transistors.
(11) Oxide Formation During Ion Bombardement
of Small Silicon Structures
D. Krüger, P. Formanek, E. Pippel, J. Woltersdorf, E. Bugiel, R. Kurps, G. Weidner
Journal of Vacuum Science and Technology
B 22 (3), 1179 (2004)
The kinetics of high dose oxygen implantation and of
surface sputtering in silicon are investigated by atomic force microscopy, transmission electron microscopy, transmission electron holography, and electron
energy-loss spectroscopy. The implantation was performed into accurately defined submicrometer areas.
The behavior of the erosion rate as a function of the
implantation dose proved to be nonmonotonic. After
native oxide sputtering, a period dominated by (i) implantation of oxygen and (ii) induced oxide formation
with volume increase takes place, causing a maximum
surface step around the bombarded area of about 1.1 to
1.3 nm at bombardment doses below 2 x 1016 O+ cm -2.
Subsequently, higher doses cause a sputtering of the
surface with a sputter yield of about 0.32 Si atoms/
O+. Electron holography revealed the double layer
character of the implanted region, and electron energy-loss spectroscopy, especially near the relevant SiL23 ionization edge, identified these two layers which
are (i) amorphous silicon oxide and (ii) amorphized silicon. Electron energy-loss line scans show the oxygen
distribution inside the implanted areas with a lateral
resolution of about 1-2 nm. It was found that the interface between the oxidized layer and the amorphized
silicon sharpens with increasing implantation dose.
(12) Some Open Issues on Internetworking for
the Next Generation
P. Langendörfer, V. Tsaoussidis
Computer Communications 27 (10), 908 (2004)
In this survey we focus on open issues of the wireless
Internet. Our main intention is to elaborate what has to
be done to integrate mobile devices in the Internet in
such way that users do not experience any difference
between wireless and fixed connections. We concentrate on the layers on top of IP, i.e. transport protocols, middleware platforms and applications. We pro-
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
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vide an overview of existing solutions and a discussion
of open issues and promising research directions is
given for each of these fields.
(13) Solid State Reaction between Pr and SiO2
Studied by Photoelectron Spectroscopy and
ab initio Calculations
G. Lupina, J. Dabrowski, P. Formanek, D. Schmeißer, R. Sorge, C. Wenger, P. Zaumseil, H.-J. Müssig
Materials Science in Semiconductor Processing
7 (4-6), 215 (2004)
We report on the structural and electrical properties of
Pr-based high-k dielectric fi lms fabricated by solid-state reaction between metallic Pr and SiO2 underlayers.
A non-destructive depth profi ling using synchrotron radiation excited photoelectron spectroscopy (SR-PES),
X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) were employed to examine the chemical composition and microstructure. Ab
initio calculations were done to gain insight into the physical processes involved. SR-PES results indicate that
Pr deposition at room temperature (RT) leads to the formation of a Pr silicide and a Pr oxide, what is in good
agreement with the scenario expected from ab initio
calculations. As revealed by TEM and electrical measurements, oxidation of the reacted structures, followed
by annealing, results in a stacked dielectric composed
of a SiO2-based buffer with an enhanced permittivity
and a Pr silicate fi lm with a high dielectric constant. The
leakage current density of 10−4 A/cm2 was measured
for stacks with capacitance equivalent thickness (CET)
of 1.5 nm prepared by evaporation of the Pr layer on
a 1.8 nm SiO2 fi lm, followed by oxidation in air ambient
and annealing in N2 atmosphere. The capacitance-voltage (C-V) curves exhibit a large flatband voltage (VFB )
shift indicating the presence of a positive charge in the
stack. Switching away from the Al contacts to Au gate
electrodes introduces a significant reduction of the VFB
by 1.3 eV, what is much more than the change expected from the work function difference between Al and
Au (~0.9 eV). This in turn implies that VFB is strongly affected by the gate interface electrode.
(14) A 64-Point Fourier Transform Chip for High
Speed Wireless LAN Application Using
OFDM
K. Maharatna, E. Grass, U. Jagdhold
IEEE Journal of Solid State Circuits 39 (3), 484
(2004)
Published Papers
In this paper, we present a novel fi xed-point 16-bit wordwidth 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a
wireless LAN baseband processor. The 64-point FFT
is realized by decomposing it into a two-dimensional
structure of 8-point FFTs. This approach reduces the
number of required complex multiplications compared
to the conventional radix-2 64-point FFT algorithm. The
complex multiplication operations are realized using
shift-and-add operations. Thus, the processor does not
use a two-input digital multiplier. It also does not need
any RAM or ROM for internal storage of coeffi cients.
The proposed 64-point FFT/IFFT processor has been
fabricated and tested successfully using our in-house
0.25-µm BiCMOS technology. The core area of this chip
is 6.8 mm2. The average dynamic power consumption
is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-toparallel (i.e., when all input data are available in parallel
and all output data are generated in parallel) 64-point
FFT computation in 23 cycles. These features show that
though it has been developed primarily for application
in the IEEE 802.11a standard, it can be used for any
application that requires fast operation as well as low
power consumption.
(15) Fast Nondestructive Technique to Determine
the Content of Components in a Strain-Compensated Crystalline Ternary Alloy
A.Y. Nikulin, P. Zaumseil
Journal of Applied Physics 95, 5249 (2004)
The x-ray Bragg diffraction intensity profile for a model strain-compensated structure consisting of a thin
SiGe alloy layer grown on a thick Si substrate is derived using a Laplace transform interpretation of the
kinematical approximation of x-ray diffraction theory.
It is shown that in the case of fully strain-compensated crystals a simplified x-ray phase-retrieval technique can be applied to determine the alloy composition
from this x-ray diffraction data. An experimental intensity profile from an almost perfectly unstrained SiGe:
C/Si structure is analyzed using this method.
(16) Stability and Electronic Properties of Silicates in the System SiO2-Pr2O3-Si(001)
D. Schmeißer, H.-J. Müssig
Journal of Physics Condensed Matter 16, 153
(2004)
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Pr2O3 is one of the most promising hetero-oxides that
are the candidates of choice to replace SiO2 as the
gate dielectric material for sub-0.1 µm CMOS technology. In order to enable process integration, however,
hetero-oxides require substantial characterization. In
particular, the basic interaction mechanisms at the interface to the silicon substrate are the key issues. A
solid knowledge of these mechanisms is required to
address reliability arguments. The challenges in material science are to understand the chemical bonding
of the hetero-oxides and Si on a microscopic scale.
We report on the specific variations in the electronic
structure which are evident in the valence band features around resonant excitation at the Pr 4d threshold. We also determine the valence band discontinuities at the Pr2O3/Si(001) interface and follow the
changes in the surface potentials to develop a band
scheme, a prerequisite to understanding the properties of charge transport across that interface.
We studied Pr2O3 /Si(001) interfaces by synchrotron
radiation photoelectron spectroscopy and by ab initio
calculations. We show that the interface formed during
molecular-beam epitaxy under the oxygen partial pressure above 1×10 –8 mbar consists of a mixed Si-Pr oxide,
such as (Pr2O3 )(SiO) x (SiO2) y. Neither an interfacial SiO2
nor an interfacial silicide is formed. The silcate formation is driven by a low energy of O in a PrOSi bond and
by the strain in the subsurface SiOx layer. We expect that
this natural interfacial Pr silicate will facilitate the integration of the high-k dielectric Pr2O3 into future complementary metal-oxide-semiconductor technologies.
(17) Pr2O3 / Si(001) Interface Reactions and Stability
Resonant photoelectron spectroscopy (PES) at the
Pr4 d and O1 s absorption edges is used to study the
electronic properties at the interface of epitaxially
grown Pr2O3 on Si(001). In the electronic structure of
bulk Pr2O3, the valence band (VB) states are predominant of Pr 6s and O2p atomic parentage. The contribution of Pr4f states is identified from the strong increase of the VB features at the Pr4 d resonances. The
data at the O1s edge are caused by Raman scattering
and resonant Auger decay and reflect the existence of
charge transfer (CT) complexes. These complexes are
the consequence of a mixed valency caused by ligandto-Pr4f charge transfer states. The decrease of their
intensity is attributed to an increase in covalent bandwidth between the ligand (O2p, Si3 p) and Pr4f states.
The CT complexes, originally localized now, become
broadened and form gap states which fill the gap towards a metallic density of states. The metallic phase may be hindered upon alloying with SiO2 or other
oxides.
D. Schmeißer, J. Dabrowski, H.-J. Müssig
Materials Science and Engineering B 109, 30
(2004)
We show that an interfacial silicate is formed in a natural way between Si(001) and the deposited Pr2O3 fi lm if
a sufficient amount of oxygen is provided during deposition, as during electron beam evaporation from Pr6O11
source. We provide arguments from results of ab initio
calculations and we present a ternary phase diagram of
the Pr-O-Si system obtained for epitaxial fi lms from nondestructive depth profi ling data acquired by synchrotron
radiation and photo-electron spectroscopy (SR-PES) at
the undulator beam line U49/2-PGM2. The composition
of the interfacial layer is (Pr2O3 )(SiO) x (SiO2) y with x+y
between 2 and 6 and depends on the growth conditions and distance from the substrate. No interfacial
SiO2 and no interfacial silicide is formed during growth.
The ternary phase diagram indicates that this non-stoichiometric pseudobinary alloy is stable on Si up to high
temperatures, without phase separation into Pr2O3 and
SiO2. Therefore, a complete re-engineering of the CMOS
process may be not necessary.
(18) Silicate Layer Formation at Pr 2O3 /Si(001)
Interfaces
D. Schmeißer, H.-J. Müssig, J. Dabrowski
Applied Physics Letters 85, 88 (2004)
128
(19) Pr4f Occupancy and VB/CB Band Offsets of
Pr2O3 at the Interface to Si (001) and SiC
(0001) Surfaces
D. Schmeißer, H.-J. Müssig
Materials Science in Semiconductor Processing
7, 221 (2004)
(20) Structure and Thickness-dependent Lattice Parameters of Ultrathin Epitaxial Pr2O3
Films on Si(001) Studied by SR-GIXRD
T. Schröder, T.-L. Lee, J. Zegenhagen, C. Wenger, P. Zaumseil, H.-J. Müssig
Applied Physics Letters 85 (7), 1229 (2004)
Pr2O3 grown heteroepitaxially on Si(001) is a promising candidate for applications as a high-k dielectric
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in future silicon-based microelectronics devices. The
technologically important thickness range from 1 to
10 nm has been investigated by synchrotron radiation-grazing incidence x-ray diffraction. The oxide film
grows as cubic Pr2O3 phase with its (101) plane on the
Si (001) substrate in form of two orthogonal rotation
domains. Monitoring the evolution of the oxide unit-cell
lattice parameters as a function of film thickness from
1 to 10 nm, the transition from almost perfect pseudomorphism to bulk values is detected.
perties of atomic layer and box-profile doped (standard) HBTs were compared, showing peak fT and f max
for the ALD HBT of 113 and 127 GHz, and of 108 and
123 GHz for the standard HBT, respectively. The internal base sheet resistances (RSBi) for the ALD and
standard HBTs were comparable, indicating very similar active B dose for both doping variants. The HBT results demonstrate the capability of atomic layer processing for doping of advanced devices, with critical
requirements for dose and location control.
(21) Formation of Heavily P-doped Si Epitaxial
Films on Si(100) by Multiple Atomic-Layer
Doping Technique
(23) Recombination Activity and Electrical Levels
of Dislocations in p-type SiGe Structures:
Impact of Copper Contamination and Hydrogenation
Y. Shimamune, M. Sakuraba, J. Murota, B. Tillack
Applied Surface Science 224 (1-4), 202
(2004)
Phosphorus (P) incorporation process during Si epitaxial growth by SiH 4 reaction in ultraclean low-pressure chemical vapor deposition (CVD) and the electrical characteristics of the heavily P-doped epitaxial Si
film on Si(100) have been investigated. Si layer growth
on the P layer formed on Si(100) at 500°C at SiH 4 partial pressure of 6 Pa is observed when the surface P
amount becomes below 7x1014 cm -2. It is also found
that about 1.1x1014 cm -2 P atoms segregate onto the
Si surface and the other desorbs. On the other hand,
by lowering the Si growth temperature to 450°C and
increase in the SiH 4 partial pressure to 220 Pa, P incorporation occurs and about 1.5x1014 cm -2 P atoms
are buried at the initial position without segregation.
By using the multiple atomic-layer doping technique,
very low-resistive heavily P-doped epitaxial Si film on
Si(100) can be formed with effective suppression of
the electrically inactive P formation.
(22) High Performance SiGe:C HBTs Using Atomic
Layer Base Doping
B. Tillack, Y. Yamamoto, D. Knoll, B. Heinemann,
P. Schley, B. Senapati, D. Krüger
Applied Surface Science 224, 55 (2004)
We applied atomic layer processing for base doping of
high performance SiGe:C heterojunction bipolar transistors (HBTs) fabricated within a 0.25 mm BiCMOS
technology. B atomic layer doping (ALD) was performed at 400°C during an interruption of the epitaxial
SiGe:C base layer deposition. Atomic level dopant location and dose control was achieved. Electrical pro-
O.F. Vyvenko, M. Kittler, W. Seifert
Journal of Applied Physics 96 (11), 6425 (2004)
The impact of copper contamination and subsequent
hydrogenation on recombination activity and hole-trap
levels of misfi t dislocations were investigated in p-type
Si/Si 0.98Ge0.02/Si structures. In the as-grown (noncontaminated) samples, dislocations were found to exhibit very low recombination activity, detectable with the
electron-beam-induced current technique only at low
temperatures. Deep-level transient spectroscopy revealed a dislocation-related hole-trap level at Et = Ev +
0.2 eV. The position of the observed level is close to the
theoretically predicted hole-trap state of the intrinsic
stacking fault of a dissociated dislocation. Contamination with a low copper concentration [5 (parts per 109 )
ppb] gave rise to a large increase of the recombination activity of the dislocations and to the appearance
of another dislocation-related defect level at Et = Ev +
0.32 eV. Hydrogenation of the samples by a treatment
with an acid solution and subsequent reverse-bias anneal
at 380 K resulted in the evolution of the levels of substitutional copper and its complexes with hydrogen.
(24) First Investigation of MIM Capacitors Using
Pr2O3 Dielectrics
C. Wenger, J. Dabrowski, P. Zaumseil, R. Sorge,
P. Formanek, G. Lippert, H.-J. Müssig
Materials Science in Semiconductor Processing
7 (4-6), 227 (2004)
Metal-insulator-metal (MIM) capacitors with Pr2O3 as
high-k material have been investigated for the first
time. We varied the thickness of the Pr2O3 layers as
well as the bottom electrode material. The layers are
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characterised using X-ray photoelectron spectroscopy
(XPS), X-ray diffraction (XRD), transmission electron
microscopy (TEM) and secondary ion mass spectroscopy (SIMS). Preliminary information on the interaction of
water with the fi lms was obtained from XPS and ab initio pseudopotential calculations. The electrical characterisation shows that Pr2O3 MIM capacitors can provide
higher capacitance densities than Si3N4 MIM capacitors
while still maintaining comparable voltage coeffi cients
of capacitance. The Pr2O3 dielectric material seems to
be suitable for use in silicon RF applications.
(25) Circuit Applications of High-Performance
SiGe:C HBTs Integrated in BiCMOS Technology
W. Winkler, J. Borngräber, B. Heinemann, H. Rücker,
R. Barth, J. Bauer, D. Bolze, E. Bugiel, J. Drews, K.-E.
Ehwald, T. Grabolla, U. Haak, W. Höppner, D. Knoll,
D. Krüger, B. Kuck, R. Kurps, S. Marschmeyer, H.H.
Richter, P. Schley, D. Schmidt, R. Scholz, B. Tillack,
D. Wolansky, H.-E. Wulf, Y. Yamamoto, P. Zaumseil
Applied Surface Science 224 (1-4), 297 (2004)
Carbon-doped SiGe (SiGe:C) bipolar devices have
been developed and integrated in to a 0.25 µm CMOS
platform. The resulting SiGe:C BiCMOS technology offers a wide spectrum of active and passive devices for
wireless and wired communication systems. A highperformance variant of the bipolar transistor has been
derived from the standard transistors by reduction of
some transistor dimensions. With these alterations,
fT and f max of the bipolar transistors reaches 120 and
140 GHz, respectively. Circuit applications of the devices are demonstrated. Static and dynamic divider
circuits have a maximum input frequency of 62 and 72
GHz, respectively. Integrated LC oscillators with frequencies up to 60 GHz are also demonstrated.
(26) Carbon and Boron in Heavily Doped SiGe:C/
Si Epilayers Studied by FTIR
V.D. Akhmetov, O. Lysytskiy, Y. Yamamoto,
H. Richter
Electrochemical Society Proceedings Vol.
2004-07, 269 (2004)
(27) Nitrogen in Thin Silicon Wafers Determined
by Infrared Spectroscopy
V.D. Akhmetov, O. Lysytskiy, H. Richter
Electrochemical Society Proceedings Vol.
2004-05, 109 (2004)
130
(28) HICUM Modeling of SiGe-HBTs Fabricated in
Wafer Bonded SOI Substrates
A. Chakravorty, B. Senapati, G. Dalapati, R. Garg,
C.K. Maiti, G.A. Armstrong, H.S. Gamble, P. Ashburn and H.A.W. El Mubarek
Proc. International Conference on Computers
and Devices for Communication, 42 (2004)
(29) Accurate Modeling of SiGe:C HBTs using
Adaptive Neuro-Fuzzy Inference System
A. Chakravorty, R.F. Scholz, B. Senapati, D. Knoll,
A. Fox, R. Garg, C.K. Maiti
Proc. ISTDM, 264 (2004)
(30) Electrical Deactivation and Diffusion of
Boron in Preamorphized Ultrashallow Junctions: Interstitial Transport and F co-implant Control
B. Colombeau, A.J. Smith, N.E.B. Cowern,
W. Lerch, S. Paul, B.J. Pawlak, F. Christiano,
X. Hebras, D. Bolze, C. Ortiz, P. Pichler
Technical Digest IEDM, 971 (2004)
(31) Preface
J. Dabrowski, H.-J. Müssig
Materials Science in Semiconductor Processing
7 (4-6), 165 (2004)
(32) Ab Initio Study of Pr Oxides for CMOS Technology
J. Dabrowski, V. Zavodinsky
Proc. NIC Symposium, 171 (2004)
(33) Transistors and Atoms
J. Dabrowski, H.-J. Müssig, E.R. Weber,
W. Schröter
Challenges in Process Simulation / ed. by
J. Dabrowski, E.R. Weber, Berlin, Springer Verlag, 1-38 (2004)
(34) Model-driven Design of the WIN Platform
J. deMeer
Proc. ICSSEA, ISSN: 1637-5033, Vol. 3 (2004)
(35) High-Level Behavioral SDL Model for the
IEEE 802.15.3. MAC Protocol
D. Dietterle, I. Babanskaja, K. Dombrowski,
R. Kraemer
Proc. WWIC 2004, Febr. 05-07, 2004, Frankfurt
(Oder), Germany. - Berlin, Springer, 165 (2004)
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Erschienene Publikationen
(36) Mapping of High-Level SDL Models to Efficient Implementations for TinyOS
D. Dietterle, J. Ryman, K. Dombrowski, R. Kraemer
Proc. EUROMICRO Symposium on Digital System
Design, IEEE Computer Society, 402 (2004)
(37) A Two Mask Complementary LDMOS Module Integrated in a 0.25 µm SiGe:C BiCMOS Platform
K.-E. Ehwald, A. Fischer, F. Fürnhammer,
W. Winkler, B. Senapati, R. Barth, D. Bolze,
B. Heinemann, D. Knoll, H. Rücker, D. Schmidt,
I. Shevchenko, R. Sorge, H.-E. Wulf
Proc. ESSDERC, 121 (2004)
(38) Bluetooth Indoor Localization System
G. Fischer, B. Dietrich, F. Winkler
Proc. 1st Workshop on Positioning, Navigation
and Communication 2004, Hannoversche Beiträge zur Nachrichtentechnik, 01, 147 (2004)
(39) Cost-Effective Integration of an FN-programmed Embedded Flash Memory into a
0.25 µm RF-BiCMOS Technology
A. Fox, K.-E. Ehwald, P. Schley, R. Barth,
S. Marschmeyer, V.E. Stikanov, A. Gromovyy,
A. Hudyryev
Proc. International Conference on Microelectronics, 463 (2004)
(40) Spectroscopic Ellipsometry for In-Line Process Control of SiGe:C HBT Technology
O. Fursenko, J. Bauer, P. Zaumseil, D. Krüger,
A. Goryachko, Y. Yamamoto, K. Köpke, B. Tillack
Proc. ISTDM 2004, Abstract book, 53 (2004)
(41) A DC – 10 GHz Amplifier With Digital Offset
Correction
H. Gustat
Proc. ISTDM 2004, Abstract book, 73 (2004)
(42) A Fully-Integrated Low-Power Low-Jitter
Clock Synthesizer with 1.2 GHz Tuning Range
in SiGe:C BiCMOS
H. Gustat, F. Herzel, I. Shevchenko
Proc. ISTDM 2004, Abstract book, 270 (2004)
(43) Complementary SiGe BiCMOS
B. Heinemann, J. Drews, D. Knoll, R. Kurps,
S. Marschmeyer, H. Rücker, W. Winkler,
Y. Yamamoto
Published Papers
Electrochemical Society Proc. SiGe: Materials,
Processing, and Devices : The 1st International
Symposium, Vol. 2004-07, 25 (2004)
(44) A Low-Parasitic Collector Construction for
High-Speed SiGe:C HBTs
B. Heinemann, R. Barth, D. Bolze, J. Drews, P. Formanek, T. Grabolla, U. Haak, W. Höppner, D. Knoll,
B. Kuck, R. Kurps, K. Köpke, S. Marschmeyer,
H.H. Richter, H. Rücker, P. Schley, D. Schmidt, W.
Winkler, D. Wolansky, H.-E. Wulf, Y. Yamamoto
Technical Digest IEDM, 251 (2004)
(45) Jitter and Phase-Noise in Oscillators and
Phase-Locked Loops
F. Herzel, W. Winkler, J. Borngräber
Proc. SPIE, Fluctuations and Noise, Vol. 5473
(2004)
(46) Standardization of Defect Characterization
Technique in Annealed CZ Si
N. Inoue, K. Moriya, K. Kashima, R. Takeda,
V. Akhmetov, O. Lysytskiy, K. Nakashima
Proc. 4th International Symposium on Advanced
Science and Technology of Silicon Materials,
123 (2004)
(47) Kristallines Si für Solarzellen: Status und
Herausforderungen
M. Kittler
Abhandlungen der Leibniz-Sozietät, Vol. 15, 69
(2004)
(48) Silicon-based Light Emission After Ion Implantation
M. Kittler, T. Arguirov, W. Seifert
Proc. SPIE, Optoelectronic Integration on Silicon, Vol. 5357, 164 (2004)
(49) Die minimal erzielbare Rekombinationsaktivität von Versetzungen in Silicium:
Schlussfolgerungen für Solarzellen und für
perspektivische auf Si basierende Lichtemitter
M. Kittler, W. Seifert
Freiberger Siliciumtage 2003, in: Freiberger Forschungshefte: Werkstofftechnologie, B 327, 89
(2004)
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
131
Erschienene Publikationen
Published Papers
(50) A Modular, Low-Cost SiGe:C BiCMOS Process
Featuring High-FT and High-BV CEO Transistors
(57) A 16-Bit CORDIC Rotator for High-Speed
Wireless LAN
K. Maharatna, A. Troya, S. Banerjee, E. Grass,
M. Krstic
Proc. IEEE PIMRC (2004)
D. Knoll, B. Heinemann, R. Barth, K. Blum,
J. Borngräber, J. Drews, K.-E. Ehwald, G. Fischer,
A. Fox, T. Grabolla, U. Haak, W. Höppner, F. Korndörfer, B. Kuck, S. Marschmeyer, H.H. Richter,
H. Rücker, P. Schley, D. Schmidt, R.F. Scholz,
B. Senapati, B. Tillack, W. Winkler, D. Wolansky,
C. Wolf, H.-E. Wulf, Y. Yamamoto, P. Zaumseil
Proc. BCTM, 241 (2004)
(58) Virtually Scaling-Free Adaptive CORDIC rotator
(51) Remote Operations: A Middleware and Distributed Systems Architecture for Satellite
On-Board Wireless Communication
(59) A Cordic Like Processor for Computation of
Arctangent and Absolute Magnitude of a
Vector
R. Kraemer, K. Dombrowski, D. Dietterle, P. Langendörfer, M. Methfessel
Proc. Data Systems in Aerospace, Session 3B
(2004)
K. Maharatna, A. Troya, M. Krstic, E. Grass,
U. Jagdhold
Proc. International Symposium on Circuits and
Systems, Vol. II, 713 (2004)
(52) GALS Baseband Processor for WLAN
M. Krstic, E. Grass
Proc. 4 th ACiD-WG Workshop (2004)
( 53) GALSification of IEEE 802.11a Baseband
Processor
M. Krstic, E. Grass
Proc. 14th International Workshop on Power
and Timing Modeling, Optimization and Simulation, Springer Verlag, LNCS Series 3254, 258
(2004)
K. Maharatna, A. Troya, S. Banerjee, E. Grass
Proc. of IEEE Computers & Digital Techniques,
Vol. 151, no. 6 (2004)
(60) Ultrathin Dielectric Films Grown by Solid
Phase Reaction of Pr with Thermal SiO2
H.-J. Müssig, J. Dabrowski, C. Wenger, G. Lupina,
R. Sorge, P. Formanek, P. Zaumseil, D. Schmeißer
Materials Research Society Symposium Vol.
811, 253 (2004)
(61) High-k Dielectrics: The Example of Pr2O3
H.-J. Osten, J. Dabrowski, H.-J. Müssig, A. Fissel,
V. Zavodinsky
Challenges in Process Simulation, Springer Verlag Berlin, 259 (2004)
(54) A Location Aware Revocation Approach
D. Kulikowski, P. Langendörfer, K. Piotrowski
Informatik , Bd. 2, GI-LNI (2004)
(55) Plasma – A Middleware for Location-Based
Services: Design, Implementations and Lessons Learned
P. Langendörfer, O. Maye, Z. Dyka, R. Sorge,
R. Winkler, R. Kraemer
Middleware for Communication, John Wiley &
Sons, 305 (2004)
(56) PLASMADS: Smart Mobiles Meet Intelligent
Environments
P. Langendörfer, H. Maass, T. Falck
Proc. 4th Workshop on Applications and Services
in Wireless Networks, IEEE Press (2004)
132
(62) Applying Position Prediction as a Means for
Performance-Tuning in Location-Aware Platforms
A. Post, P. Langendörfer, R. Kraemer
Proc. 1st Workshop on Positioning, Navigation and Communication, Hannoversche Beiträge zur Nachrichtentechnik, Shaker Verlag, 179
(2004)
(63) Moneta: An Anonymity Providing Lightweight Payment System for Mobile Devices
K. Piotrowski, P. Langendörfer, D. Kulikowski
Proc. 2nd International Workshop for Technology,
Economy, Social and Legal Aspects of Virtual
Goods (2004)
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Erschienene Publikationen
(64) Ensuring Anonymity in e-commerce Systems
Using a Hidden Identity Approach: Discussion of Problems and Solutions
K. Piotrowski, P. Langendörfer, O. Maye
Proc. 7th International Conference on Electronic
Commerce Research (2004)
Published Papers
63 rd ARFTG Conference Digest, On Wafer Characterization, 83 (2004)
(72) Macro Model of Power RF LDMOSFET
(65) SiGe HBT Design for High-Frequency Applications
B. Senapati, K.-E. Ehwald, I. Shevchenko, F. Fürnhammer
Proc. International Conference on Communications, Devices and Intelligent Systems, 23
(2004)
H. Rücker, B. Heinemann, R. Barth, D. Knoll,
P. Schley, R. Scholz, B. Tillack, W. Winkler
Proc. ISTDM, 61 (2004)
(73) Application of the VBIC Model for SiGe:C
Heterojunction Transistors
(66) Advances in SiGe HBT Technology in Europe
H. Rücker, W. Winkler
Proc. Compound Semiconductor IC Symposium,
13 (2004)
(67) Integration of High-Performance SiGe:C HBTs
with Thin-Film SOI CMOS
H. Rücker, B. Heinemann, R. Barth, D. Bolze,
J. Drews, O. Fursenko, T. Grabolla, U. Haak,
W. Höppner, D. Knoll, S. Marschmeyer, N. Mohapatra, H.H. Richter, P. Schley, D. Schmidt,
B. Tillack, G. Weidner, D. Wolansky, H.-E. Wulf,
Y. Yamamoto
Technical Digest IEDM, 239 (2004)
(68) The System Behavioral Model of IEEE 802.15.3
Mac Protocol – Design and Profiling
J. Ryman, D. Dietterle, K. Dombrowski, P. Bubacz
Proc. 2nd International Workshop on DiscreteEvent System Design (2004)
(69) Analysis of Microwave Noise Sources in
150 GHz SiGe HBTs
P. Sakalas, M. Schröter, R.F. Scholz, H. Jiang,
M. Racanelli
IEEE RFIC Digest, 291 (2004)
(70) A 1 GHz AGC Amplifier in BiCMOS with 3µs
Settling-Time for 802.11a WLAN
K. Schmalz
Proc. IEEE Norchip, 289 (2004)
(71) Advanced Technique for Broadband on-Wafer RF Device Characterization
B. Senapati, R.F. Scholz, D. Knoll, B. Heinemann,
A. Chakravorty
Proc. International Conference on Mixed Design
of Integrated Circuits and Systems, 94 (2004)
(74) Self-Consistent Characterization of Gate
Controlled Diodes for CMOS Technology
Monitoring
R. Sorge, P. Schley, K.-E. Ehwald
Proc. ESSDERC, 389 (2004)
(75) Modular Processor: A Flexible Library of
ASIC Modules
Z. Stamenkovic, G. Panic, U. Jagdhold, H. Frankenfeldt, K. Tittelbach-Helmrich, G. Schoof,
R. Kraemer
Proc. IASTED International Conference on Applied Simulation and Modelling, Acta Press, 428
(2004)
(76) Atomic Level Control of SiGe Epitaxy and
Doping
B. Tillack, Y. Yamamoto, J. Murota
Proc. SiGe: Materials, Processing, and Devices:
Proceedings of the 1st International Symposium,
Honolulu, ECS Vol. 2004-07, 803 (2004)
(77) A 117 GHz LC-Oscillator in SiGe:C BiCMOS
Technology
W. Winkler, J. Borngräber, B. Heinemann
Proc. ISTDM, 71 (2004)
(78) LC-Oscillators Above 100 GHz in SiliconBased Technology
W. Winkler, J. Borngräber, B. Heinemann
Proc. ESSCIRC, 131 (2004)
R.F. Scholz, F. Korndörfer, B. Senapati, A. Rumiantsev
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
133
Eingeladene Vor träge
Invited Presentations
(79) High-Frequency Low-Noise Amplifiers and
Low-Jitter Oscillators in SiGe:C BiCMOS
Technology
W. Winkler, J. Borngräber, F. Herzel, B. Heinemann, R. Scholz
Proc. SPIE Fluctuations and Noise, Vol. 5470,
185 (2004)
(6)
J. deMeer, P. Langendörfer
Colloquium des Fachbereichs Informatik der Universität Passau, June 29, 2004, Germany
(7)
(80) 60 GHz Transceiver Circuits in SiGe:C BiCMOS
Technology
(8)
(2)
(3)
Determination of Optical Constants Using
Swing Curves
J. deMeer
UML/Java Workshop für Embedded und Realtime Systeme, TFH Berlin, July 29, 2004, Germany
(10) Silicon-based Light Emission After Ion Implantation: Role of Defects and of Crystalline Perfection
Presentations of the IHP PLASMA Platform
MEDman – Ubiquitous Medical Assistance
Mobile Nutzung von Sensornetzwerken auf
der PLASMA-Plattform
J. deMeer, P. Langendörfer
Ringvorlesung des Instituts für Informatik und
Gesellschaft der Universität Freiburg (Breisgau),
June 28, 2004, Germany
134
BiCMOS Integration of High-Speed
SiGe:C HBTs
Mobile Application Patterns – Real Time or
Ubiquity?
J. deMeer
EUREKA MEDEA+ Board Paris, May 25 and June
3, 2004, France
(5)
(9)
B. Heinemann, H. Rücker
Workshop Advances in Modeling and Simulation
of Semiconductor Devices, Berlin, July 12-16,
2004, Germany
J. deMeer, R. Kraemer
Visit of the Middleware Research Labs – Toronto, Montreal, Nashville, March 27 – April 4,
2004, Canada and USA
(4)
Complementary SiGe BiCMOS
B. Heinemann, J. Drews, D. Knoll, R. Kurps,
S. Marschmeyer, H. Rücker, W. Winkler, Y. Yamamoto
SiGe: Materials, Processing, and Devices : The
1st International Symposium, Honolulu, October
03-08, 2004, Hawaii, USA
Eingeladene Vorträge
Invited Presentations
J. Bauer, U. Haak, G. Drescher
Lithography Workshop, Pommelsbrunn, September 17-19, 2004, Germany
Analog Design Challenges in Ultrawide-Band
Technology
B. Dietrich
International Union of Radio Science, Landesausschuss in der Bundesrepublik Deutschland,
Kleinheubacher Tagung Miltenberg, September
24, 2004, Germany
W. Winkler, J. Borngräber, F. Herzel, H. Gustat,
B. Heinemann, F. Korndörfer
Proc. ESSCIRC, 83 (2004)
(1)
Mobile Nutzung von Sensornetzwerken auf
der PLASMA-Plattform
M. Kittler
10 th Internat. Conf. on “Extended Defects in
Semiconductors” EDS 2004, Moscow, September 2004, Russia
(11) Si-basierte Lichtemitter für die On-chipDatenübertragung
M. Kittler
FhG Inst. für Photonische Mikrosysteme, Dresden, October 7, 2004, Germany
(12) Energy Efficient Middleware Design in Support of User Privacy
P. Langendörfer
Panel Discussion at 4th Workshop on Applications and Services in Wireless Networks, Boston, August 09-11, 2004, USA
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Eingeladene Vor träge
Invited Presentations
(13) PLASMA: A Location-, Privacy- and Energyaware Middleware Platform
(21) Defect Engineering und Wafer Design in der
Siliziumtechnologie
P. Langendörfer
North Eastern University, Boston, August 12,
2004, USA
H. Richter
Freiburger Materialforschungszentrum, Freiburg,
July 9, 2004, Germany
(14) Are There Alternatives to Silicon Based Technology
(22) Si Crystal Growth and Defect Engenieering
W. Mehr
EMRS 2004 Spring Meeting Strasbourg, May 26,
2004, France
H. Richter
The 4th Int. Symp. On Advanced Science and
Technology of Silicon Materials, Kona, Hawaii,
November 22-26, 2004, USA
(15) Mikroelektronik – der große Schritt in
kleinste Welten
(23) SiGe HBT Design for High-Frequency Applications
W. Mehr
Tag der Wissenschaft an der Europa-Universität
Frankfurt (Oder), November 10, 2004, Germany
H. Rücker, B. Heinemann, R. Barth, D. Knoll,
P. Schley, R. Scholz, B. Tillack, W. Winkler
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
(16) Alternative SOI-Strukturen
H.-J. Müssig
Siltronic AG Burghausen, March 25, 2004,
Germany
(17) Neue Materialien in der Mikroelektronik –
Trends und Anforderungen
H.-J. Müssig
Institut für Ionenstrahlphysik und Materialforschung Forschungszentrum Rossendorf, March
29, 2004, Germany
(18) Welche Rolle spielen neue Materialien in
der Mikroelektronik?
H.-J. Müssig
Tag der offenen Tür im IHP, Frankfurt (Oder),
September 04, 2004, Germany
(19) Atomically Controlled Impurity Doping in
Si-Based CVD
J. Murota, M. Sakuraba, B. Tillack
MRS Spring Meeting 2004, San Francisco, April
12-16, 2004, USA
(20) IHP – Institut für innovative Mikroelektronik
H. Richter
Hochschulinformationstag der TFH Wildau, May 7,
2004, Germany
(24) Advances in SiGe HBT Technology in Europe
H. Rücker, W. Winkler
Compound Semiconductor IC Symposium,
Monterey, October 23-28, 2004, USA
(25) A Comparative SR-GIXRD, STM and LEED Study
of the Structural Properties of Pr2O3 Epilayers on Si(001) and Si(111)
T. Schröder, H.-J. Müssig
Hahn Meitner Institute Berlin, April 2004, Germany
(26) Modern Synchrotron Radiation Grazing Incidence Diffraction Studies: The Example
of Epitaxial Pr2O3 Layers on Si(001) and
Si(111)
T. Schröder, T.L. Lee, L. Libralesso, J. Zegenhagen, C. Wenger, P. Zaumseil, H.-J. Müssig
Ecole Centrale de Lyon, Laboratory of Electronical Engineering, Lyon, July 2004, France
(27) Atomic Level Control of SiGe Epitaxy and
Doping
B. Tillack
University of Hannover, Institute for Semiconductor Devices and Electronic Materials, July 8,
2004, Germany
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
135
Vor träge
Presentations
(28) High-Performance, Low-Cost SiGe:C BiCMOS
Technology
(2)
B. Tillack, D. Knoll, B. Heinemann, K.-E. Ehwald,
H. Rücker, R. Barth, P. Schley, W. Winkler
Semicon Europe, Munich, April 20-22, 2004,
Germany
(29) High-Performance, Low-Cost SiGe:C BiCMOS
Technolog y
V.D. Akhmetov, O. Lysytskiy, Y. Yamamoto,
H. Richter
SiGe: Materials, Processing, and Devices: The
1st International Symposium, Honolulu, October
03-08, 2004 Hawaii, USA
(3)
B. Tillack, D. Knoll, B. Heinemann, K.-E. Ehwald,
H. Rücker, R. Barth, P. Schley, W. Winkler
STS Session: SiGe/SOI/Strained Si: From
Growth to Device Properties, International Congress Center Munich, April 21, 2004, Germany
(30) Atomic Level Control of SiGe Epitaxy and
Doping
(4)
(5)
(1)
(6)
V.D. Akhmetov, O. Lysytskiy, H. Richter
9 th Augustusburg Conference of Advanced
Science, Das Silicium-Zeitalter: Silicium für Mikroelektronik, Photvolatik und Photonik, Augustusburg, September 23-25, 2004, Germany
136
Accurate Modeling of SiGe:C HBTs using
Adaptive Neuro-Fuzzy Inference System
A. Chakravorty, R.F. Scholz, B. Senapati,
D. Knoll, A. Fox, R. Garg, C.K. Maiti
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
(7)
Nitrogen in Thin Silicon Wafers Determined
by Infrared Spectroscopy
Effects of Various Ci/Ti and Co/TiN Layer
Stacks and the Silicide Rapid Thermal Process Conditions on Cobalt Silicide Formation
S. Buschbaum, O. Fursenko, D. Bolze, D. Wolansky, V. Melnik, J. Nieß, W. Lerch
MAM 2004 – Materials for Advanced Metallization, Brussels, March 2004, Belgium
P. Zaumseil
HREDAMM, Zakopane, June 13-17, 2004, Poland
Vorträge
Presentations
Bestimmung der optischen Eigenschaften
des Fotoresists für die FotolithographieWellenlängen durch Swingoptimierung
J. Bauer, U. Haak, G. Drescher
3 rd Workshop Ellipsometrie, Stuttgart, February
23-25, 2004, Germany
W. Winkler, B. Heinemann, D. Knoll
European Gallium Arsenide and other Compound
Semiconductors Application Symposium, Amsterdam, October 11-12, 2004, The Netherlands
(32) High Resolution X-Ray Characterization of
SiGe:C Structures for High Frequency Microelectronics Applications
Silicon-based Light Emission after Ion Implantation
T. Arguirov, M. Kittler, W. Seifert, A. Fischer
9 th Augustusburg Conference of Advanced
Science, Das Silicium-Zeitalter: Silicium für
Mikroelektronik, Photvolatik und Photonik, Augustusburg, September 23-25, 2004, Germany
B. Tillack, Y. Yamamoto, J. Murota
SiGe: Materials, Processing, and Devices: The
1st International Symposium, Honolulu, October
03-08, 2004, Hawaii, USA
(31) Application of SiGe:C BiCMOS to Wireless
and Radar
Carbon and Boron in Heavily Doped SiGe:C/Si
Epilayers Studied by FTIR
Electrical Deactivation and Diffusion of
Boron in Preamorphized Ultrashallow Junctions: Interstitial Transport and F co-implant Control
B. Colombeau, A.J. Smith, N.E.B. Cowern,
W. Lerch, S. Paul, B.J. Pawlak, F. Christiano,
X. Hebras, D. Bolze, C. Ortiz, P. Pichler
IEDM 2004, San Francisco, December 13-15,
2004, USA
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Vor träge
(8)
(9)
MEDman – Ubiquitous Medical Assistance
J. deMeer
EUREKA MEDEA+ Board Paris, June 03, 2004,
France
Model-driven Design of the WIN Platform
Presentations
B. Heinemann, D. Knoll, H. Rücker, D. Schmidt,
I. Shevchenko, R. Sorge, H.-E Wulf
ESSDERC 2004, Leuven, September 21-23,
2004, Belgium
(16) Bluetooth Indoor Localization System
J. deMeer
17èmes Journées Internationales «Génie Logiciel &
Ingénierie de Systèmes et leurs Applications», Paris – November 30 - December 2, 2004, France
G. Fischer, B. Dietrich, F. Winkler
1st Workshop on Positioning, Navigation and
Communication 2004, Hannover, March 26,
2004, Germany
(10) How to Achieve Security by Architecturing
Middleware Supporting Mobile Applications
(17) SiGe:C-BiCMOS-Technologie als Basis für
UWB-Transceiver
J. deMeer
IST 2004 Conference – Workshop on Emerging
Security Technology, Den Haag, November 1517, 2004, The Netherlands
G. Fischer, B. Heinemann, R. Kraemer
Öffentliche Diskussionssitzung des Fachausschusses 7.2 der ITG zu Ultra Wide Band – Technologien und mögliche Anwendungen, KampLintfort, November 11, 2004, Germany
(11) Deployment of Sensor Networks to medical
and other Business Application Domains
J. deMeer
IST 2004 Conference – Workshop on Research
Collaboration between Canada and Europe, Den
Haag, November 15-17, 2004, The Netherlands
(18) Application of Electron Holography in BiCMOS
Technology
(12) High-Level Behavioral SDL Model for the
IEEE 802.15.3 MAC Protocol
P. Formanek, B. Heinemann, M. Kittler, D. Krüger, R. Kurps, A. Orchowski, A. Ourmazd,
W.-D. Rau, H. Rücker, P. Schwander, B. Tillack,
P. Zaumseil
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
D. Dietterle, I. Babanskaja, K. Dombrowski,
R. Kraemer
WWIC 2004, Frankfurt (Oder), February 05-07,
2004, Germany
(19) Application of Electron Holography to Extended Defects: Schottky Barriers at NiSi2
Precipitates in Silicon
(13) Mapping of High-Level SDL Models to Efficient Implementations for TinyOS
D. Dietterle, J. Ryman, K. Dombrowski, R. Kraemer
EUROMICRO Symposium on Digital System Design, Rennes, August 31- September 03, 2004,
France
(14) Integrated RF LDMOS
K.-E. Ehwald
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(15) A Two Mask Complementary LDMOS Module Integrated in a 0.25 µm SiGe:C BiCMOS Platform
K.-E. Ehwald, A. Fischer, F. Fürnhammer,
W. Winkler, B. Senapati, R. Barth, D. Bolze,
P. Formanek, M. Kittler
10 th Internat. Conf. on Extended Defects in Semiconductors – EDS 2004, Moscow, September,
2004, Russia
(20) Flash Integration
A. Fox
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(21) Cost-effective Integration of an FN-programmed Embedded Flash Memory into a
0.25 µm RF-BiCMOS Technology
A. Fox, K.-E. Ehwald, P. Schley, R. Barth,
S. Marschmeyer, V.E. Stikanov, A. Gromovyy,
A Hudyryev
The ICM 2004 International Conference on Microelectronics, Tunis, December 6-8, 2004, Tunisia
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
137
Vor träge
Presentations
(22) Optimization of Anti-reflective Coating
PECVD SiOxNy for Lithography Application
(29) Standardization of Defect Characterization
Technique in Annealed CZ Si
O. Fursenko, J. Bauer, B. Kuck, A. Penkov
3 rd Workshop Ellipsometrie, Stuttgart, February
23-25, 2004, Germany
N. Inoue, K. Moriya, K. Kashima, R. Takeda,
V.D. Akhmetov, O. Lysytshiy, K. Nakashima
4th International Symposium on Advanced Science and Technology of Silicon Materials, Kona,
November 22-26, 2004, USA
(23) Spectroscopic Ellipsometry for In-Line Process Control of SiGe:C HBT Technology
O. Fursenko, J. Bauer, P. Zaumseil, D. Krüger,
A. Goryachko, Y. Yamamoto, K. Köpke, B. Tillack
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
(24) A DC – 10 GHz Amplifier With Digital Offset
Correction
H. Gustat
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
(25) A Fully-Integrated Low-Power Low-Jitter
Clock Synthesizer with 1.2 GHz Tuning Range
in SiGe:C BiCMOS
(30) Oxygen, Nitrogen, Intrinsic Point Defects
and their Interaction in Defect Generation
for Internal Gettering
G. Kissinger
Physikalisches Kolloquium der BTU Cottbus,
November 11, 2004, Germany
(31) Direct Evidence of Internal Schottky Barriers at NiSi2 Precipitates in Si by Electron
Holography
M. Kittler
Gordon Conference on Defects in Semiconductors, New London, July 2004, USA
(32) Raumladung an NiSi2-Präzipitaten in n-Si
H. Gustat, F. Herzel, I. Shevchenko
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
M. Kittler, P. Formanek
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder, April 2004, Germany
(26) A Low-Parasitic Collector Construction for
High-Speed SiGe:C HBTs
(33) Silicon-based Light Emission after Ion Implantation
B. Heinemann, R. Barth, D. Bolze, J. Drews,
P. Formanek, T. Grabolla, U. Haak, W. Höppner, D. Knoll, B. Kuck, R. Kurps, K. Köpke,
S. Marschmeyer, H.H. Richter, H. Rücker, P.
Schley, D. Schmidt, W. Winkler, D. Wolansky,
H.-E. Wulf, Y. Yamamoto
IEDM 2004, San Francisco, December 13-15,
2004, USA
M. Kittler, T. Arguirov, A. Fischer, W. Seifert
E-MRS Spring Meeting 2004, Strasbourg, May
24-28, 2004, France
(34) Silicon-based Light Emission After Ion Implantation
M. Kittler, T. Arguirov, W. Seifert
Photonics West 2004 – Optoelectronic Integration
on Silicon, San Jose, January 24-29, 2004, USA
(27) High-performance HBT Modules in BiCMOS
B. Heinemann
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(28) Jitter and Phase-Noise in Oscillators and
Phase-locked Loops
F. Herzel, W. Winkler, J. Borngräber
2nd International Symposium on Fluctuations and
Noise, Maspalomas, Gran Canaria, May 26-28,
2004, Spain
138
(35) Passivierbarkeit von Cu-kontaminierten Versetzungen in p-Si
M. Kittler, W. Seifert, O. Vyvenko
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder, April 2004, Germany
(36) Enhanced Relaxation of SiGe Layers by He
Implantation Supported by In-Situ Ultrasonics Treatments
V.P. Kladko, V. Melnik, Ya. M. Olikh, V. Popov,
B. Romanjuk, V.M. Yuchimchuk, D. Krüger
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Vor träge
Presentations
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
(44) Integrierte drahtlose Systeme und integrierte Radarsysteme der Zukunft
(37) 5 GHz Transceiver in a SiGe:C BiCMOS Technology
R. Kraemer
Vortrag zum Tag der offenen Tür im IHP, Frankfurt (Oder), September 04, 2004, Germany
J. Klatt, N. Fiebig
Workshop Analogschaltungen, Freiburg, March
11-12, 2004, Germany
(38) Polycrystalline Si Solar Cells With DLC Antireflection Coatings
N. Klyui, V. Litovchenko, M. Kittler, W. Seifert
International Conference on Polycrystalline Semiconductors, POLYSE 2004, Potsdam, September 2004, Germany
(39) A Modular, Low-Cost SiGe:C BiCMOS Process Featuring High-FT and High-BV CEO
Transistors
D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Borngräber, J. Drews, K.-E. Ehwald, G. Fischer, A. Fox,
T. Grabolla, U. Haak, W. Höppner, F. Korndörfer,
B. Kuck, S. Marschmeyer, H.H. Richter, H. Rücker, P. Schley, D. Schmidt, R.F. Scholz, B. Senapati,
B. Tillack, W. Winkler, D. Wolansky, C. Wolf, H.-E.
Wulf, Y. Yamamoto, P. Zaumseil
BCTM Montreal 2004, September 11-17, 2004,
Canada
(40) SGB25VD Low Cost BiCMOS Approach
D. Knoll
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(41) Wireless Engine
R. Kraemer
Ringvorlesung Schwerpunkte der Informatik, Humboldt Universität Bln, January 29, 2004, Germany
(42) Chip-Entwicklung am IHP
R. Kraemer
Seminar Technischer Bereich, DESY Zeuthen,
February 24, 2004, Germany
(43) Der Bluetooth-Koffer: Intelligentes Gepäck
für eine erhöhte Sicherheit
R. Kraemer
Ringvorlesung Das Internet und seine Anwendungen (III), BTU Cottbus, May 04, 2004, Germany
(45) Remote Operations: A Middleware and Distributed Systems Architecture for Satellite
On-Board Wireless Communication
R. Kraemer, K. Dombrowski, D. Dietterle, P. Langendörfer, M. Methfessel
DASIA 2004, Data Systems in Aerospace, Nice,
June 28-July 01, 2004, France
(46) GALS Baseband Processor for WLAN
M. Krstic, E. Grass
4th ACiD-WG Workshop, Turku, June 28-29,
2004, Finland
(47) GALSification of IEEE 802.11a Baseband
Processor
M. Krstic, E. Grass
14th International Conference on PATMOS 2004,
Santorini, September 15-17, 2004, Greece
(48) A Location Aware Revocation Approach
D. Kulikowski, P. Langendörfer, K. Piotrowski
Mobile Computing und Medien Kommunikation
im Internet, University of Ulm, September 23,
2004, Germany
(49) PLASMADS: Smart Mobiles Meet Intelligent
Environments
P. Langendörfer, H. Maass, T. Falck
4th Workshop on Applications and Services
in Wireless Networks, Boston, August 09-11,
2004, USA
(50) A Combined Synchrotron X-Ray Diffraction
and STM Study of the Structural Properties
of Ultra-Thin Pr2O3 Layers on Si(111)
L. Libralesso, T. Schröder, T.L. Lee, I. Joumard,
J. Zegenhagen, H.-J. Müssig
E-MRS Spring Meeting 2004, Strasbourg, May
24-28, 2004, France
(51) Dependence of Structural and Electrical
Properties of Pr and La Oxides on Growth,
Annealing and Storage Conditions
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
139
Vor träge
Presentations
G. Lippert, J. Dabrowski, P. Formanek, V. Melnik,
R. Sorge, Ch. Wenger, P. Zaumseil, H.-J. Müssig
16th International Vacuum Congress, Venice,
June 28 - July 02, 2004, Italy
(52) Deposition Conditions and Post Treatment
of High-k Praseodymium and Lanthanum
Oxide Dielectrics
G. Lippert, J. Dabrowski, P. Formanek, V. Melnik,
R. Sorge, Ch. Wenger, P. Zaumseil, H.-J. Müssig
206th Meeting of the Electrochemical Society,
Honolulu, October 03-08, 2004, Hawaii, USA
(58) Thin Dielectric Films Grown by Solid Phase
Reaction of Pr with Thermal SiO2
H.-J. Müssig, J. Dabrowski, C. Wenger, G. Lupina,
R. Sorge, P. Formanek, P. Zaumseil, D. Schmeißer
MRS Spring Meeting, San Francisco, April 12-16,
2004, USA
(59) Moneta: An Anonymity Providing Lightweight Payment System for Mobile Devices
K. Piotrowski, P. Langendörfer, D. Kulikowski
2nd GI/IFIP Workshop on Virtual Goods, Ilmenau,
May 27 - 29, 2004, Germany
(53) Properties of Pr-silicate High-k Dielectrics
Formed by Solid-State Reaction Between Pr
and SiO2
(60) Ensuring Anonymity in e-commerce Systems
Using a Hidden Identity Approach: Discussion of Problems and Solutions
G. Lupina
Deutscher MBE-Workshop, Braunschweig, October 12, 2004, Germany
K. Piotrowksi, P. Langendörfer, O. Maye
7th International Conference on Electronic Commerce Research, Dallas, June 10-13, 2004,
USA
(54) Solid State Reaction between Pr and SiO2
Studied by Photoelectron Spectroscopy and
ab initio Calculations
G. Lupina, J. Dabrowski, P. Formanek, D. Schmeißer, R. Sorge, C. Wenger, P. Zaumseil, H.-J. Müssig
E-MRS Spring Meeting, Strasbourg, May 24-28,
2004, France
(55) A CORDIC Like Processor for Computation
of Arctangent and Absolute Magnitude of a
Vector
K. Maharatna, A. Troya, M. Krstic, E. Grass,
U. Jagdhold
Int. Symposium on Circuits and Systems, ISCAS
2004, Vancouver, May 23 - 26, 2004, Canada
(56) Wann werden die Grenzen der Mikroelektronik erreicht? – Zukünftige Entwicklungstrends
W. Mehr
Tag der offenen Tür im IHP, Frankfurt (Oder),
September 04, 2004, Germany
(57) TCP/IP Processor for Wireless
M. Methfessel
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
140
(61) Applying Position Prediction as a Means for
Performance-tuning in Location-aware Platforms
A. Post, P. Langendörfer, R. Kraemer
1st Workshop on Positioning, Navigation and
Communication 2004 (WPNC’04), Hannover,
March 26, 2004, Germany
(62) Mechanische Eigenschaften von ultradünnen Si-, GeSi- und GeSi:C-MBE Schichten auf
(100) Siliziumsubstraten
R. Ries, A. Richter, B. Tillack
5. Workshop Rasterkraftmikroskopie in der
Werkstoffwissenschaft, Dresden, February 2627, 2004, Germany
(63) Integration of High-Performance SiGe:C
HBTs with Thin-Film SOI CMOS
H. Rücker, B. Heinemann, R. Barth, D. Bolze,
J. Drews, O. Fursenko, T. Grabolla, U. Haak,
W. Höppner, D. Knoll, S. Marschmeyer, N. Mohapatra, H.H. Richter, P. Schley, D. Schmidt,
B. Tillack, G. Weidner, D. Wolansky, H.-E. Wulf,
Y. Yamamoto
IEDM 2004, San Francisco, December 13-15,
2004, USA
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Vor träge
(64) The System Behavioral Model of IEEE 802.15.3
Mac Protocol – Design and Profiling
J. Ryman, D. Dietterle, K. Dombrowski, P. Bubacz
2nd International Workshop on Discrete-Event
System Design, DESDes ‘04, Dychow, September 15-17, 2004, Poland
(65) A 1 GHz AGC Amplifier in BiCMOS With 3 µm
Settling-Time for 802.11a WLAN
K. Schmalz
IEEE Norchip 2004, Oslo, November 8-9, 2004,
Norway
(66) High Reactivity of Pr on Oxide Covered
4H-SiC
D. Schmeißer, G. Lupina, H.-J. Müssig
E-MRS Spring Meeting 2004, Strasbourg, May
24-28, 2004, France
(67) Pr4f Occupancy and VB/CB Band Offsets of
Pr2O3 at the Interface to Si (001) and SiC
(0001) Surfaces
D. Schmeißer, H.-J. Müssig
E-MRS Spring Meeting 2004, Strasbourg, May
24-28, 2004, France
(68) Design Kit and MPW Service
R.F. Scholz
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(69) Advanced Technique for Broadband on-Wafer
RF Device Characterization
R.F. Scholz, F. Korndörfer, B. Senapati, A. Rumiantsev
63 rd ARFTG Conference, On Wafer Characterization, Ft. Worth, June 11, 2004, USA
(70) The Heteroepitaxial Systems Pr2O3 /Si(001)
and Pr2O3/Si(111): Structure and Strain in
Rare Earth Oxide Epilayers on Si
T. Schröder, T.L. Lee, L. Libralesso, C. Wenger,
P. Zaumseil, H.-J. Müssig
GDR Meeting, Grenoble, June 2004, France
Presentations
(71) Structure and Thickness-Dependent Lattice
Parameters of Ultrathin Epitaxial Pr2O3 Films
on Si(001) Studied by SR-GIXRD
T. Schröder, T.-L. Lee, J. Zegenhagen, C. Wenger,
P. Zaumseil, H.-J. Müssig
Frühjahrstagung der Deutschen Physikalischen
Gesellschaft, Regensburg, March 08-12, 2004,
Germany
(72) A Grazing Incidence X-Ray Diffraction Study
of Ultra-Thin Praseodymium Oxide Layers
on Si (001): From Pseudomorphism to Bulk
Behavior
T. Schröder, T.L. Lee, L. Libralesso, J. Zegenhagen, Ch. Wenger, P. Zaumseil, H.-J. Müssig
E-MRS Spring Meeting 2004, Strasbourg, May
24-28, 2004, France
(73) Defekte und Rekombinationseigenschaften
in n-leitendem HEM-Material
W. Seifert, M. Kittler, G. Jia
Arbeitstreffen ASIS-Verbundprojekt, Ochsenfurt,
September 2004, Germany
(74) Modelling and RF Characterisation
B. Senapati
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(75) Macro Model of Power RF LDMOSFET
B. Senapati, K.-E. Ehwald, I. Shevchenko,
R. Scholz, F. Fürnhammer
International Conference on Communications,
Devices and Intelligent Systems, Kolkata, January 8-10, 2004, India
(76) VBIC Model for SiGe:C Bipolar Technology
B. Senapati, R.F. Scholz, D. Knoll, B. Heinemann,
A. Chakravorty
11th International MIXDES Conference, Szczecin,
June 24-26, 2004, Poland
(77) Self-Consistent Characterization of Gate Controlled Diodes for CMOS Technology Monitoring
R. Sorge, P. Schley, K.-E. Ehwald
ESSDERC 2004, Leuven, September 21-23,
2004, Belgium
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
141
Vor träge
Presentations
(78) Modular Processor: A Flexible Library of
ASIC Modules
Z. Stamenkovic, G. Panic, U. Jagdhold, H. Frankenfeldt, K. Tittelbach-Helmrich, G. Schoof,
R. Kraemer
IASTED International Conference on Applied
Simulation and Modelling – ASM 2004, Rhodes,
June 28-30, 2004, Greece
(79) Atomic Layer Processing for Steep and Shallow Doping Profiles
B. Tillack, D. Bolze, R. Kurps, D. Wolansky,
Y. Yamamoto, W. Mehr
Workshop RTP & Blitzlampen-Temperverfahren,
Rossendorf, October 21, 2004, Germany
(80) Advances in SiGe HBT Technology in Europe
B. Tillack, D. Knoll, B. Heinemann, K.-E. Ehwald, H.
Rücker, R. Barth, P. Schley, W. Winkler, W. Mehr
Das Silicium-Zeitalter: Silicium für Mikroelektronik, Photovoltaik und Photonik, Augustusburg,
September 23-25, 2004, Germany
(81) Recombination Activity and Electrical Levels
of Clean and Copper Contaminated Dislocations in p-type Si
O.F. Vyvenko, M. Kittler, W. Seifert, M.V. Trushin
10 th Internat. Conf. on Extended Defects in Semiconductors EDS 2004, Moscow, September
2004, Russia
(82) First Investigations of MIM Capacitors Using
Pr2O3 Dielectrics
C. Wenger
Frühjahrstagung der DPG, Regensburg, March
11, 2004, Germany
(83) Electrical Properties of Praseodymium-Silicate Films for High-K Gate Applications
C. Wenger, J. Dabrowski, G. Lupina, P. Zaumseil,
R. Sorge, P. Formanek, G. Lippert, H.-J. Müssig
Workshop of Dielectrics in Microelectronics
2004, Cork, June 28-30, 2004, Ireland
(84) First Investigation of MIM Capacitors Using
Pr2O3 Dielectrics
C. Wenger, J. Dabrowski, P. Zaumseil, R. Sorge,
P. Formanek, G. Lippert, H.-J. Müssig
E-MRS Spring Meeting, Strasbourg, May 24-28,
2004, France
142
(85) High-Performance RF Circuits
W. Winkler
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
(86) DüseF: Bedeutung und Stand der Forschung
im IHP
W. Winkler
Presentation for Project Preparation „Drahtlose Übertragung von Sensordaten im Fahrzeug
(DüseF)“, Stuttgart Gerlingen, January 26, 2004,
Germany
(87) Millimeterwellen-Schaltungen: Bedeutung
und Stand der Forschung im IHP
W. Winkler
Workshop MMIC-Technologie in der KFZ-Radarsensorik, Wolfsburg, January 30, 2004, Germany
(88) Frontend-Anforderungen für 77 GHz UMRR
Sensor
W. Winkler
Workshop MMIC-Technologie in der KFZ-Radarsensorik, Wolfsburg, February 20, 2004, Germany
(89) Vorstellung der IHP Technologie und der IHP
Schaltungstechnik
W. Winkler
Meeting „Radarsysteme für die Automobilindustrie“, Ilmenau, April 4, 2004, Germany
(90) Vorstellung des IHP und Grundschaltungen
für 60 und 76 GHz Radarsysteme
W. Winkler
Treffen zur Zusammenarbeit zwischen TU-Ilmenau (TUI), DaimlerChrysler (DC), MEDAV und IHP,
Ilmenau, April 30, 2004, Germany
(91) Kostengünstige MMICs für 77 GHz mit der
IHP SiGe:C Technologie
W. Winkler
Workshop „MMIC-Technologie in der KFZ-Radarsensorik“, Wolfsburg, June 16, 2004, Germany
(92) Cost-Effective MMICs for 77 GHz Automotive Radar with IHP SiGe:C Technology
W. Winkler
Workshop „MMIC-Technologie in der KFZ-Radarsensorik“, Wolfsburg, Septrmber 28, 2004, Germany
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Berichte
(93) LC-Oscillator for 94 GHz Automotive Radar
System Fabricated in SiGe:C BiCMOS Technology
W. Winkler, J. Borngräber
European Gallium Arsenide and other Compound
Semiconductors Application Symposium, Amsterdam, October 11-12, 2004, The Netherlands
(94) A 117 GHz LC-Oscillator in SiGe:C BiCMOS
Technology
Berichte
Reports
(1)
SSMSC – Smart Secure Mass Storage Cards
E. Charbonnier, J. deMeer
Project Full Proposal to EU EUREKA/MEDEA+,
23.09.2004
(2)
W. Winkler, J. Borngräber, B. Heinemann
2nd ISTDM 2004, Frankfurt (Oder), May 16-19,
2004, Germany
Ab Initio Investigation of Pr-related High-K
Dielectrics for CMOS Technology Development
J. Dabrowski
Project HFO06: Application for Computing Time
on IBM Regatta and Cray, Progress Report
07.2003-04.2004
(95) LC-Oscillators Above 100 GHz in SiliconBased Technology
W. Winkler, J. Borngräber, B. Heinemann
ESSCIRC 2004 – European Solid-State Circuits
Conference, Leuven, September 20-23, 2004,
Belgium
Repor ts
(3)
Verbundprojekt „Wireless Internet-Zellular“
Machbarkeitsstudie: Applikationen und Spezifikation ihrer zugehörigen Demonstratoren
C. Deist, O. Maye et al., 2004
(96) High-Frequency Low-Noise Amplifiers and
Low-Jitter Oscillators in SiGe:C BiCMOS Technology
W. Winkler, J. Borngräber, F. Herzel, B. Heinemann, R. Scholz
2nd International Symposium on Fluctuations and
Noise, Maspalomas, Gran Canaria, May 26-28,
2004, Spain
(4)
J. deMeer
Contribution to Work Item AP2.1 (Architectural
Principles) of the WINcell Project, 30.08.2004
(5)
(97) 60 GHz Transceiver Circuits in SiGe:C BiCMOS
Technology
W. Winkler, J. Borngräber, F. Herzel, H. Gustat,
B. Heinemann, F. Korndörfer
ESSCIRC 2004 – European Solid-State Circuits
Conference, Leuven, September 20-23, 2004,
Belgium
(99) A Complex X-Ray Characterization of Epitaxially Grown High-K Gate Dielectrics
P. Zaumseil, T. Schröder
XTOP 2004, Prague, September 07-10, 2004,
Czech Republic
Begriffsdefinitionen für AP2.1 „Tragfähige
Architektur“
J. deMeer
Contribution to Work Item AP2.1 (Architectural
Principles) of the WINcell Project, 06.08.2004
(6)
RESIDUAL – Reflective System Design for
Human Life Assistancy
J. deMeer
EU STREP Proposal on FET open Call FP6-2002IST-C, 17.12.2004
(98) Reliability and Process Qualification
P. Zaumseil
Workshop High-Performance SiGe:C BiCMOS for
Wireless and Broadband Communication, Frankfurt (Oder), September 30, 2004, Germany
On Designing Consistent Middleware Platforms, Version 0.2
(7)
Zwischenbericht
K. Dombrowski
BASUMA Projekt, 2004
(8)
Zwischenbericht Gesamtprojekt
K. Dombrowski
BASUMA Projekt, 2004
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
143
Berichte
(9)
Repor ts
Efficient Implementations of Cryptographic
Routines – A Review and Performance Analysis of Various Approaches
Z. Dyka, F. Vater, O. Maye, P. Langendörfer,
R. Kraemer
Technical Report 01/04, BTU Cottbus, 2004
(10) 4th Periodic Report and Final Report HERCULAS Project
P. Formanek, M. Kittler, 2004
(11) Single-Chip Lösung für bandbreiteneffizientes drahtloses Kommunikationssystem
E. Grass, K. Tittelbach-Helmrich, H. Frankenfeldt, N. Fiebig
BMBF-Projekt 01 BU 054, Schlussbericht: On
the Single-Chip Implementation of a Hiperlan/2
and IEEE 802.11a Capable Modem, 2004
(17) Raumladung an NiSi2-Präzipitaten in n-Si
M. Kittler, P. Formanek
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder, April 2004
(18) Passivierbarkeit von Cu-kontaminierten Versetzungen in p-Si
M. Kittler, W. Seifert, O. Vyvenko
Arbeitstreffen ASIS-Verbundprojekt, Grosse Ledder, April 2004
(19) Ergebnisbericht Wireless Internet – zellular
B. Lehmann, P. Langendörfer et al., 2004
(20) Design of PAL and Voice Optimisation for WLAN
A. Lunn, K. Tittelbach-Helmrich, F.M. Krause,
T. Becker, B. Cheetham, M. Kuhn, M. Methfessel, A. Ettafagh, M. Secall, M. Spegel
WinDECT Deliverable D3.2, 2004
(12) Abschlussbericht
E. Grass, N. Fiebig, K. Tittelbach-Helmrich
IBMS2 (BMBF) Single-Chip Lösung für bandbreiteneffizientes drahtloses Kommunikationssystem, 2004
(13) Zwischenbericht 1
E. Grass, F. Herzel, M. Piz, J.P. Ebert
WIGWAM (BMBF) Schichtenübergreifender Entwurf eines Höchstgeschwindigkeits-WLAN: Konzept, SoC-Implementierung und Demonstrator,
im Rahmen der Leitinnovation „Mobile Internet“,
16.02.2004
(21) Shallow-Trench RIE – Verfahrensentwicklung
H. H. Richter, S. Marschmeyer, S. Günther, H. Silz
Abschlussbericht zum Forschungs- und Entwicklungsvertrag vom 17.06.2004 zwischen
ZMD Dresden GmbH & Co. KG und IHP Frankfurt
(Oder) GmbH
(22) Solid State Reaction Between Pr and SiO2
Studied by Photoelectron Spectroscopy
D. Schmeißer, G. Lupina, H.-J. Müssig
BESSY II – Status Report, 2004
(23) Defekte und Rekombinationseigenschaften in
n-leitendem HEM-Material, Zwischenbericht
(14) Zwischenbericht 2
E. Grass, F. Herzel, M. Piz, J.P. Ebert
WIGWAM (BMBF) Schichtenübergreifender Entwurf eines Höchstgeschwindigkeits-WLAN: Konzept, SoC-Implementierung und Demonstrator,
im Rahmen der Leitinnovation „Mobile Internet“,
12.08.2004
(15) Final Report to Siltronic AG (contractual period March 15 – June 30, 2004)
G. Kissinger, 2004
(16) Final Report to Siltronic AG (contractual peri-
W. Seifert, M. Kittler, G. Jia
Arbeitstreffen ASIS-Verbundprojekt, Ochsenfurt,
Sept. 2004
(24) 506746 – WINDECT STP D2.2 Technical Specification of 173, Demonstration System
M. Spegel, A. Lunn, F.-M. Krause, T. Wellhausen, K. Tittelbach-Helmrich, P. Reinhardt,
B. Cheetham
WINDECT Wireless LAN with Integration of
Professional-Quality DECT Telephony Report,
2004
od July 01 – December 31, 2004)
G. Kissinger, 2004
144
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Monographien
Monographien
Monographs
(1)
(8)
Materials Science in Semiconductor Processing , Vol. 7 (2004)
Papers presented at the E-MRS 2004 Spring
Meeting Symposium C: New Materials in Future Silicon Technology
Eds. J. Dabrowski, H.-J. Müssig
Elsevier, 2004
Monographs
Entwurf und Implementierung einer DSPbasierten IEEE 802.11a-Synchronisationseinheit
R. Kothe
Diplomarbeit, BTU Cottbus, 2004
(9)
Providing Trust in E-commerce Systems
(Especially in Wired/Wireless Networks)
D. Kulikowski
Diplomarbeit, University Zielona Gora, 2004
(10) Wired/Wireless Internet Communications
(2)
Predictive Simulation of Semiconductor Processing – Status and Challenges
Eds. J. Dabrowski, E.R. Weber
Springer Series in Materials Science, Berlin,
Springer Verlag 2004
(3)
Energy-Efficient Communication in Ad Hoc
Wireless Local Area Networks
J.P. Ebert
Dissertation, TU Berlin, 2004
(4)
TEM-Holographie an Bauelementestrukturen
der Mikroelektronik
SiGe: Materials, Processing, and Devices:
Proceedings of the 1st International Symposium
Eds: D. Harame, J. Boquet, J. Cressler,
D. Houghton, H. Iwai, T.-J. King, G. Masini,
J. Murota, K. Rim, B. Tillack
Proceedings Electrochemical Society Vol.
2004-07 (2004)
(6)
Integration von Standard-AAA-Technologien
in eine Plattform für ortssensitive Dienste
unter besonderer Berücksichtigung mobiler
Endgeräte
K. Jendrusch
Diplomarbeit, TFH Wildau, 2004
(7)
(11) Towards Privacy Negotiation for Internet
Services: Design and Prototyping of Basic
Concepts
M. Maaser
Diplomarbeit, BTU Cottbus, 2004
P. Formanek
Dissertation, BTU Cottbus, 2004
(5)
P. Langendörfer, M. Liu, I. Matta; V. Tsaoussidis
(Eds.)
2nd International Conference WWIC 2004, Frankfurt (Oder), Proceedings, Springer Verl., 2004.(LNCS; 2957)
Das Silicium-Zeitalter: Silicium für Mikroelektronik, Photovoltaik und Photonik
Ed. M. Kittler
Abstracts, 9 th Augustusburg Conference of
Advanced Science, Augustusburg (Sachsen),
23.-25. Sept. 2004
(12) Proceedings of the First International SiGe
Technology and Devices Meeting (ISTDM
2003): From Materials and Process Technology to Device and Circuit Technology, Nagoya
University Symposion, Japan. Jan. 15-17, 2003
ed. by J. Murota, B. Tillack, M. Caymax,
J. Sturm, Y. Yasuda, S. Zaima
Applied Surface Science 224 (1-4) (2004)
(13) Design and Implementation of an Off-Line
E-Cash Scheme
K. Piotrowski
Diplomarbeit, University of Zielona Góra, Faculty of Electrical Engineering, Computer Science
and Telecommunications, 2004
(14) Evaluation of Performance Impacts of Early
Handoff Detection for PLASMA Event and
Handoff Processing
A. Post
Bachelorarbeit, BTU Cottbus, 2004
(15) Gettering and Defect Engineering in Semiconductor Technology – The 10 th GADEST
Conference
Eds. H. Richter, M. Kittler
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
145
Patente
Patents
Proc. GADEST 2003, in Solid State Phenomena,
95-96, 2004, 682 pages
(16) Design and Profiling of the SystemC Behavioral Model of the MAC Protocol According to
IEEE 802.15.3
(5)
G. Lippert
IHP.257.04, DE-Patentanmeldung am 04.05.04,
AZ: 10 2004 023 135.4
(6)
J. Ryman
Diplomarbeit, University Zielona Gora, 2004
(7)
(18) Synchronization and Channel Estimation in
OFDM: Algorithms for Efficient Implementation of WLAN Systems
(8)
(9)
Verfahren und Vorrichtung zur Niedertemperaturepitaxie auf einer Vielzahl von Halbleitersubstraten
T. Grabolla, B. Tillack
IHP.256.04, DE-Patentanmeldung am 10.05.04
AZ: 10 2004 024 207.0
Schieberegister mit linearer Rückkopplung
H. Gustat
IHP.254.03, DE-Patentanmeldung am 28.01.04,
AZ: 10 2004 005 243.3
(3)
Ätzverfahren für MOS-Schichtstrukturen mit
praseodymoxidhaltigem Dielektrikum
H.-J. Müssig
IHP.261.04, DE-Patentanmeldung am 04.10.04,
AZ: 04 090 382.5
Patente
Patents
(2)
Verfahren zur Herstellung einer Lanthanoidsilikatschicht, insbesondere einer Praseodymsilikatschicht
H.-J. Müssig
IHP.259.04, DE-Patentanmeldung am 30.03.04,
AZ: 10 2004 016 320.0
A. Troya
Dissertation, BTU Cottbus, 2004
(1)
Halbleiterbauelement mit Gegensignalschaltung zum Vermeiden von Übersprechen elektronischer Baugruppen
G. Lippert
IHP.251.03, DE-Patentanmeldung am 08.04.04,
AZ: 10 2004 018 448.8
(17) Design, Simulation und Evaluierung eines
5 GHz-Low-IF-Receivers
S. Seelig
Diplomarbeit, Universität der Bundeswehr, 2004
Kondensatorstruktur
Method and Apparatus for the Determination of the Concentration of Impurities in
a Wafer
H. Richter, V.D. Akhmetov, O. Lysytskiy
IHP.260.04, EP-Patentanmeldung am 14.05.04,
AZ: 04 090 195.1
(10) Verfahren zum schrittweisen Austausch persönlicher Informationen in non-trusted Peerto-Peer Umgebungen
T. Falck, H. Maaß, K. Weidenhaupt, P. Langendörfer
PHDE30356, PCT-Anmeldung mit Philips
Vertikaler Bipolartransistor
B. Heinemann
IHP.263.04 DE-Patentanmeldung am 11.12.04,
AZ: 10 2004 061 327.3
(4)
Silizium-basierter Lichtemitter
M. Kittler, A. Fischer, T. Arguirov, W. Seifert
IHP.258.04, DE-Patentanmeldung am 14.05.04,
AZ: 10 2004 025 099.5
146
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Notizen
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Notices
147
Notizen
148
Notices
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
Wegbeschreibung zum IHP
Directions to IHP
by plane
-
per Flugzeug
-
-
-
Vom Flughafen Berlin-Tegel mit der Buslinie X9 bis
Bahnhof Berlin-Zoologischer Garten (19 Minuten);
dann mit dem RegionalExpress RE 1 bis Frankfurt
(Oder) Hauptbahnhof (ca. 1 Stunde 20 Minuten).
Vom Flughafen Berlin-Schönefeld mit dem AirportExpress oder der S-Bahnlinie S 9 bis Bahnhof Berlin-Ostbahnhof (19 bzw. 32 Minuten); dann mit dem
RegionalExpress RE 1 bis Frankfurt (Oder) Hauptbahnhof (ca. 1 Stunde).
Vom Flughafen Berlin-Tempelhof mit der U-Bahnlinie U 6 Richtung Alt-Tegel bis zur Haltestelle Friedrichstraße (11 Minuten); umsteigen in den RegionalExpress RE 1 bis Frankfurt (Oder) Hauptbahnhof
(ca. 1 Stunde 15 Minuten).
-
-
by train
-
per Bahn
-
Von den Berliner Bahnhöfen Zoologischer Garten,
Friedrichstraße, Alexanderplatz oder Ostbahnhof mit dem RegionalExpress RE 1 bis Frankfurt
(Oder) Hauptbahnhof.
per Auto
-
Über den Berliner Ring auf die Autobahn A 12 in Richtung Frankfurt (Oder)/Warschau; Abfahrt Frankfurt
(Oder) -West, an der Ampel links in Richtung Frankfurt (Oder)/Beeskow und dem Wegweiser „Technologiepark Ostbrandenburg“ folgen (ca. 1 Stunde).
From Berlin-Tegel Airport take the bus X9 to the railway station Berlin-Zoologischer Garten (19 minutes);
then take the RegionalExpress RE 1 to Frankfurt
(Oder) Hauptbahnhof (appr. 1 hour 20 minutes).
From Berlin-Schönefeld Airport take the AirportExpress or the S-Bahn line S 9 to the railway station Berlin Ostbahnhof (19 resp. 32 minutes); then
take the RegionalExpress RE 1 to Frankfurt (Oder)
Hauptbahnhof (appr. 1 hour).
From Berlin-Tempelhof Airport take the subway line U 6
in the direction Alt-Tegel to the station Friedrichstraße;
there transfer to the RegionalExpress RE 1 to Frankfurt (Oder) Hauptbahnhof (appr. 1 hour 15 minutes).
Take the train RegionalExpress RE 1 from the Berlin railway stations Zoologischer Garten, Friedrichstraße, Alexanderplatz or Ostbahnhof to Frankfurt
(Oder) Hauptbahnhof.
by car
-
Take the highway A 12 from Berlin in the direction
Frankfurt (Oder)/ Warschau (Warsaw); take exit
Frankfurt (Oder) -West, at the traffic lights turn
left in the direction Frankfurt (Oder)/Beeskow and
follow the signs to "Technologiepark Ostbrandenburg" (appr. 1 hour).
per Straßenbahn in Frankfurt (Oder)
-
Ab Frankfurt (Oder) Hauptbahnhof mit der Linie 4
in Richtung Markendorf Ort bis Haltestelle Technologiepark (14 Minuten).
by tram in Frankfurt (Oder)
-
Take the Tram 4 from railway station Frankfurt
(Oder) Hauptbahnhof in the direction Markendorf
Ort to Technologiepark (14 minutes).
JAHRESBERICHT 2004 | IHP ANNUAL REPORT
2004
IHP GmbH – Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
Phone +49.335.56 25 0
Fax
+49.335.56 25 300
www.ihp-microelectronics.com
Member of the Leibniz Association